// Contador modulo 16

module contador_mod_16(
  input  clk,up,clear,
  output reg [3:0] q,
  output cy);

 	assign cy = &q;
	
	always @(posedge clk)
	  if (clear==1 )
	    q <= 0;
	  else if (up==1)
	    q <= q + 1;
 
endmodule