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 -----------------------------------------------------------------------------
 -----------------------------------------------------------------------------
 -- File           : tb_counter_updown.vhd
 -----------------------------------------------------------------------------
 -- Description    : 
 -- --------------------------------------------------------------------------
 -- Author         : Geert Vanwijnsberghe
 -- Date           : 4/12/2006
 -- Version        : 1.0
 -- Change history : 
 ----------------------------------------------------------------------------- 
 -- This code was developed by Osman Allam during an internship at IMEC, 
 -- in collaboration with Geert Vanwijnsberghe, Tom Tassignon en Steven 
 -- Redant. The purpose of this code is to teach students good VHDL coding
 -- style for writing complex behavioural models.
 -----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity tb_counter_updown is
end entity;

architecture test of tb_counter_updown is

  type vector_out_type  is array(0 to 16) of std_logic_vector(8 downto 0);
  constant vec_out : vector_out_type := (
   "UUUUUUUUU",
   "UUUUUUUUU",
   "000000000",
   "000000000",
   "000000000",
   "000101101",
   "000101101",
   "000101110",
   "000101111",
   "000101111",
   "000101110",
   "000101101",
   "000101101",
   "011010001",
   "011010001",
   "011010010",
   "011010010"
   );

  -- add the signal declarations
  -- add code here

  
  -- add component description of the counter_updown
  -- add code here
  

  procedure GenClock (signal   clk       : out std_logic;
                      constant startlevel: in std_logic; -- '0' | '1'
                      constant CLKPeriod : in time;
                      signal   EndOfSim  : in boolean
                      ) is
  begin
      loop
        exit when EndOfSim;
        clk <= startlevel;
        wait for CLKPeriod / 2;
        exit when EndOfSim;
        clk <= not startlevel;
        wait for CLKPeriod - (CLKPeriod / 2); 
      end loop;
      wait; 
  end procedure GenClock;
  
begin

-- instantiate a 9 bit counter_updown.
-- add code here



-- apply a clock clk with a period of 10 ns starting at high level
-- add code here



main: process
begin
  d <= std_logic_vector(to_unsigned(45,9));
  rst <= '0';
  ld <= '0';
  inc <= '0';
  dec <= '0';
  wait for 25 ns;
  rst <='1';
  wait for 10 ns;
  rst <= '0';
  wait for 10 ns;
  ld <='1';
  wait for 10 ns;
  ld <='0';
  wait for 10 ns;
  inc <='1';
  wait for 20 ns;
  inc <='0';
  wait for 10 ns;
  dec <='1';
  wait for 20 ns;
  dec <='0';
  d <= std_logic_vector(to_unsigned(209,9));
  wait for 10 ns;
  inc <= '1';
  ld <= '1';
  dec <= '1';
  wait for 10 ns;
  inc <= '0';
  ld <= '0'; 
  dec <= '0';
  wait for 10 ns; 
  inc <= '1';
  dec <= '1'; 
  wait for 10 ns;
  inc <= '0';
  dec <= '0';  
  wait for 10 ns; 
  EndOfSim <= true;
  wait;
end process main;


verify: process
begin
  for i in 0 to 16 loop
    wait until falling_edge(clk);
    wait for 1 ns;
    assert q = vec_out(i)
      report "Wrong q"
      severity error;
  end loop; 
  wait;
end process verify;


end architecture;