%%%% BOOKS %%%%

@INBOOK{ostua12,
   author = "Ostua, E. and Mu\~noz, A. and Ruiz-de-Clavijo, P. and Bellido, M.~J. and Guerrero, D. and Millan, A.",
   title = "Open Development Platform for Embedded Systems",
   editor = "S.~Maad",
   booktitle = "Grid Computing -- Technology and Applications, Widespread Coverage and New Horizons",
   publisher = "InTech, Croatia",
   year = "2012",
   chapter = "14",
   pages = "311--324",
   isbn = "978-953-51-0604-3",
   doi = "10.5772/37739"
};

@BOOK{bellido06,
   author = "Bellido, M.~J. and Juan, J. and Valencia, M.",
   title = "Logic-timing Simulation and the Degradation Delay Model",
   publisher = "Imperial College Press, United Kingdom",
   year = "2006",
   isbn = "1-86094-589-9"
};

@BOOK{acosta00,
   author = "Acosta, A.~J. and Barriga, A. and Bellido, M.~J. and Juan, J. and Valencia, M.",
   title = "Temporización en Circuitos Integrados Digitales CMOS",
   publisher = "Marcombo, Barcelona (Spain)",
   year = "2000",
   isbn = "84-267-1246-0"
};

%%%% Journals %%%%
   
@article{viejo12,
	author = "J. Viejo and J.~I. Villar and J. Juan and A. Millan and E. Ostua and J. Quiros",
	title = "Long-term on-chip verification of systems with logical events scattered in time",
	journal = "Microprocessors and Microsystems",
	volume = "36",
	number = "5",
	year = "2012",
	pages = "402--408",
	publisher = "Elsevier",
	address = "United Kingdom",
	issn = "0141-9331",
	doi = "10.1016/j.micpro.2012.02.005",
};

@article{viejo11,
	author = "J. Viejo and J. Juan and M. J. Bellido and A. Millan and P. Ruiz-de-Clavijo",
	title = "Fast-convergence microsecond-accurate clock discipline algorithm for hardware implementation",
	journal = "IEEE Transactions on Instrumentation and Measurement",
	volume = "60",
	number = "12",
	year = "2011",
	pages = "3961--3963",
	publisher = "IEEE Press",
	address = "United States of America",
	issn = "0018-9456",
	doi = "10.1109/TIM.2011.2164828"
};

@article{guerrero11,
	author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and E. Ostua and J. Viejo",
	title = "Studying the viability of static CMOS gates with a large number of inputs when using separate transistor wells",
	journal = "Journal of Low Power Electronics",
	volume = "7",
	year = "2011",
	pages = "444--452", 
	issn = "1546-1998"
};

@article{millan10,
	author = "A. Millan and M.~J. Bellido and J. Juan and D. Guerrero and P. Ruiz-de-Clavijo and J. Viejo",
	title = "Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies",
	journal = "Journal of Low Power Electronics",
	volume = "6",
	year = "2010",
	pages = "93--102", 
	issn = "1546-1998"
};

@article{millan09,
	author = "A. Millan and J. Juan and M.~J. Bellido and D. Guerrero and P. Ruiz-de-Clavijo and J. Viejo",
	title = "Power dissipation associated to internal effect transitions in static CMOS gates",
	journal = "Lecture Notes in Computer Science",
	volume = "5349",
	year = "2009",
	pages = "389--398", 
	issn = "0302-9743"
};

@article{guerrero07-1,
	author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and E. Ostua and J. Viejo",
	title = "Static power consumption in CMOS gates using independent bodies",
	journal = "Lecture Notes in Computer Science",
	volume = "4644",
	year = "2007",
	pages = "404--412", 
	issn = "0302-9743"
};

@article{guerrero07-2,
	author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and E. Ostua and J. Viejo",
	title = "Improving the performance of static CMOS gates by using independent bodies",
	journal = "Journal of Low Power Electronics",
	volume = "3",
	year = "2007",
	pages = "70--77", 
	issn = "1546-1998"
};

@article{guerrero06,
	author = "D. Guerrero and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and E. Ostua and J. Viejo",
	title = "Automated performance evaluation of skew-tolerant clocking schemes",
	journal = "International Journal of Electronics",
	volume = "93",
	number = "12",
	year = "2006",
	pages = "819--842", 
	issn = "0020-7217"
};

@article{clavijo06,
	author = "P. Ruiz-de-Clavijo and J. Juan and M.~J. Bellido and A. Millan and D. Guerrero and E. Ostua and J. Viejo",
	title = "Accurate logic-level current estimation for digital CMOS circuits",
	journal = "Journal of Low Power Electronics",
	volume = "2",
	year = "2006",
	pages = "87--94", 
	issn = "1546-1998"
};

@article{clavijo05,
	author = "P. Ruiz-de-Clavijo and J. Juan and M.~J. Bellido and A. Millan and D. Guerrero and E. Ostua and J. Viejo",
	title = "Logic-level fast current simulation for digital CMOS circuits",
	journal = "Lecture Notes in Computer Science",
	volume = "3728",
	year = "2005",
	pages = "425--435", 
	issn = "0302-9743"
};

@article{millan05,
	author = "A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua and J. Viejo",
	title = "Application of Internode model to global power consumption estimation in SCMOS gates",
	journal = "Lecture Notes in Computer Science",
	volume = "3728",
	year = "2005",
	pages = "337--347", 
	issn = "0302-9743"
};

@article{millan04,
	author = "A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua",
	title = "Signal sampling based transition modeling for digital gates characterization",
	journal = "Lecture Notes in Computer Science",
	volume = "3254",
	year = "2004",
	pages = "829--837", 
	issn = "0302-9743"
};

@article{guerrero03,
	author = "D. Guerrero and G. Wilke and J.~L. Guntzel and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and A. Millan",
	title = "Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits",
	journal = "Lecture Notes in Computer Science",
	volume = "2799",
	year = "2003",
	pages = "501--510", 
	issn = "0302-9743"
};

@article{clavijo02,
	author = "P. Ruiz-de-Clavijo and J. Juan and M.~J. Bellido and A. Millan and D. Guerrero",
	title = "Efficient and fast current curve estimation of CMOS digital circuits at the logic level",
	journal = "Lecture Notes in Computer Science",
	volume = "2451",
	year = "2002",
	pages = "400--408", 
	issn = "0302-9743"
};

@article{millan02,
	author = "A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and D. Guerrero",
	title = "Characterization of normal propagation delay for Delay Degradation Model (DDM)",
	journal = "Lecture Notes in Computer Science",
	volume = "2451",
	year = "2002",
	pages = "477--486", 
	issn = "0302-9743"
};

@article{baena02,
	author = "C. Baena and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and C.~J. Jimenez and M. Valencia",
	title = "Measurement of the switching activity of CMOS digital circuits at the gate level",
	journal = "Lecture Notes in Computer Science",
	volume = "2451",
	year = "2002",
	pages = "353--362", 
	issn = "0302-9743"
};

@article{juan01,
	author = "J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and C. Baena and C.~J. Jimenez and M. Valencia",
	title = "Switching activity evaluation of CMOS digital circuits using logic timing simulation",
	journal = "IEE Electronics Letters",
	volume = "37",
	number = "9",
	year = "2001",
	pages = "555--557", 
	issn = "0013-5194"
};

@article{acosta00,
	author = "A.~J. Acosta and R. Jimenez and J. Juan and M.~J. Bellido and M. Valencia",
	title = "Influence of clocking strategies on the design of low switching-noise digital and mixed-signal VLSI circuits",
	journal = "Lecture Notes in Computer Science",
	volume = "1918",
	year = "2000",
	pages = "316--326", 
	issn = "0302-9743"
};

@article{juan00,
	author = "J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and A.~J. Acosta and M. Valencia",
	title = "Degradation delay model extension to CMOS gates",
	journal = "Lecture Notes in Computer Science",
	volume = "1918",
	year = "2000",
	pages = "149--158", 
	issn = "0302-9743"
};

@article{bellido00,
	author = "M.~J. Bellido and J. Juan and A.~J. Acosta and M. Valencia and J.~L. Huertas",
	title = "Logical modelling of delay degradation effect in static CMOS gates",
	journal = "IEE Proceedings on Circuits Devices Systems Engineering",
	volume = "147",
	number = "2",
	year = "2000",
	pages = "107--117", 
	issn = "1350-2409"
};

%%%% Conferences %%%%

%%%% 2012 %%%%

@inproceedings{ruiz12,
	author = "J. Ruiz and J.~I. Villar and M.~J. Bellido and D. Guerrero and J. Viejo and P. Ruiz-de-Clavijo and J. Juan",
	title = "Diseño e implementación de un controlador domótico reconfigurable basado en hardware y software libre",
	booktitle = "Proc. 12th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
	address = "Elche (Spain)",
	month = "September",
	year = "2012",
	pages = "161--166", 
	isbn = "978-84-695-4470-9"
};

@inproceedings{verlan12,
	author = "S. Verlan and J. Quiros",
	title = "Fast Hardware Implementations of P Systems",
	booktitle = "Proc. 13th International Conference on Membrane Computing (CMC)",
	address = "Budapest (Hungary)",
	month = "August",
	year = "2012",
	pages = "433--452", 
	isbn = "978-963-311-372-1"
};

%%%% 2011 %%%%

@inproceedings{quiros11,
	author = "J. Quiros and J. Viejo and A. Millan and A. Mu\~noz and J.~I. Villar and D. Guerrero",
	title = "Implementation of a configuration server for a hardware SNTP synchronization platform based on FPGA",
	booktitle = "Proc. 7th Southern Conference on Programmable Logic (SPL)",
	address = "Cordoba (Argentina)",
	month = "April",
	year = "2011",
	pages = "239--244", 
	isbn = "978-1-4244-8846-9"
};

@inproceedings{villar11,
	author = "J.~I. Villar and J. Juan and M.~J. Bellido and J. Viejo and D. Guerrero and J. Decaluwe",
	title = "Python as a Hardware Description Language: A Case Study",
	booktitle = "Proc. 7th Southern Conference on Programmable Logic (SPL)",
	address = "Cordoba (Argentina)",
	month = "April",
	year = "2011",
	pages = "117--122", 
	isbn = "978-1-4244-8846-9"
};

%%%% 2010 %%%%

@inproceedings{quiros10,
	author = "J. Quiros and J. Viejo and A. Mu\~noz and A. Millan and E. Ostua and J.~I. Villar",
	title = "Implementación sobre FPGA de un cliente SNTP usando MicroBlaze",
	booktitle = "Proc. 16th Iberchip Workshop (IWS)",
	address = "Iguazu Falls (Brazil)",
	month = "February",
	year = "2010",
	pages = "--"
};

@inproceedings{viejo10-1,
	author = "J. Viejo and J.~I. Villar and J. Juan and A. Millan and M.~J. Bellido and E. Ostua",
	title = "Design and implementation of a suitable core for on-chip long-term verification",
	booktitle = "Proc. 5th IEEE International Symposium on Industrial Embedded Systems (SIES)",
	address = "Trento (Italy)",
	month = "July",
	year = "2010",
	pages = "234--237", 
	isbn = "978-1-4244-5840-0"
};

@inproceedings{viejo10-2,
	author = "J. Viejo and J.~I. Villar and J. Juan and A. Millan and M.~J. Bellido and J. Quiros",
	title = "Verificación on-chip de larga duración de sistemas con eventos lógicos dispersos en el tiempo",
	booktitle = "Proc. 10th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
	address = "Valencia (Spain)",
	month = "September",
	year = "2010",
	pages = "269--276", 
	isbn = "978-84-92812-56-1"
};

@inproceedings{viejo10-3,
	author = "J. Viejo and J.~I. Villar and J. Juan and A. Millan and E. Ostua and J. Quiros",
	title = "Long-term on-chip verification of systems with logical events scattered in time",
	booktitle = "Proc. 25th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Lanzarote (Spain)",
	month = "November",
	year = "2010",
	pages = "323--326", 
	isbn = "978-84-693-7393-4"
};

%%%% 2009 %%%%

@inproceedings{guerrero09-1,
	author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and E. Ostua",
	title = "Performance Analysis of Bulk-CMOS Gates Using Separated Wells",
	booktitle = "Proc. 15th Iberchip Workshop (IWS)",
	address = "Buenos Aires (Argentina)",
	month = "March",
	year = "2009",
	pages = "54--59"
};

@inproceedings{guerrero09-2,
	author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and E. Ostua",
	title = "Delay and Power Consumption of Static Bulk-CMOS Gates Using Independent Bodies",
	booktitle = "Proc. 4th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)",
	address = "Cairo (Egypt)",
	month = "April",
	year = "2009",
	pages = "191--196", 
	isbn = "978-1-4244-4321-5"
};

@inproceedings{ostua09,
	author = "E. Ostua and M.~J. Bellido and J. Viejo and A. Millan and A. Mu\~noz and D. Guerrero",
	title = "Aplicación de Picoblaze como Emulador/Receptor de un GPS en el diseño hardware de un cliente/servidor SNTP",
	booktitle = "Proc. 9th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
	address = "Madrid (Spain)",
	month = "September",
	year = "2009",
	pages = "193--202", 
	isbn = "978-84-8138-832-9"
};

@inproceedings{viejo09-1,
	author = "J. Viejo and J. Juan and E. Ostua and M.~J. Bellido and A. Millan and A. Mu\~noz and J.~I. Villar",
	title = "Accurate and compact implementation of a hardware SNTP Client",
	booktitle = "Proc. 15th Iberchip Workshop (IWS)",
	address = "Buenos Aires (Argentina)",
	month = "March",
	year = "2009",
	pages = "504--509"
};

@inproceedings{viejo09-2,
	author = "J. Viejo and J. Juan and E. Ostua and A. Millan and P. Ruiz­-de-­Clavijo and J.~I. Villar and J. Quiros",
	title = "Implementación sobre FPGA de un cliente SNTP de bajo coste y alta precisión",
	booktitle = "Proc. 9th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
	address = "Madrid (Spain)",
	month = "September",
	year = "2009",
	pages = "359--366", 
	isbn = "978-84-8138-832-9"
};

@inproceedings{villar09-1,
	author = "J.~I. Villar and J. Juan and M.~J. Bellido",
	title = "Efficient techniques and methodologies for embedded system design using free hardware and open standards",
	booktitle = "Proc. 19th International Conference on Field Programmable Logic and Applications (FPL)",
	address = "Prague (Czech Republic)",
	month = "August",
	year = "2009",
	pages = "719--720", 
	isbn = "978-1-4244-3892-1"
};

@inproceedings{villar09-2,
	author = "J.~I. Villar and J. Juan and M.~J. Bellido and P. Ruiz­-de-­Clavijo and D.Guerrero and A. Mu\~noz",
	title = "Usando Python como HDL: Estudio comparativo de resultados basado en el desarrollo de un periférico real",
	booktitle = "Proc. 9th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
	address = "Madrid (Spain)",
	month = "September",
	year = "2009",
	pages = "33--42", 
	isbn = "978-84-8138-832-9"
};


%%%% 2008 %%%%

@inproceedings{guerrero08-1,
	author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and J. Viejo and A. Mu\~noz",
	title = "Using Independent Bodies in Bulk-CMOS Gates",
	booktitle = "Proc. 11th IEEE Symposium on Low-Power and High-Speed Chips (COOLChips)",
	address = "Yokohama (Japan)",
	month = "April",
	year = "2008",
	pages = "221"
};

@inproceedings{guerrero08-2,
	author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo, E.Ostua",
	title = "Delay and Power Consumption of Static Bulk-CMOS Gates Using Independent Bodies",
	booktitle = "Proc. 7th Journées d'études Faible Tension Faible Consommation (FTFC)",
	address = "Louvain-la-Neuve (Belgium)",
	month = "May",
	year = "2008",
	pages = "105--110"
};

@inproceedings{millan08,
	author = "A. Millan and M.~J. Bellido and J. Juan and D. Guerrero and P. Ruiz-de-Clavijo and J. Viejo",
	title = "Internal Power Dissipation of Static CMOS Gates in UDSM Technologies",
	booktitle = "Proc. 11th IEEE Symposium on Low-Power and High-Speed Chips (COOLChips)",
	address = "Yokohama (Japan)",
	month = "April",
	year = "2008",
	pages = "127"
};

@inproceedings{munoz08,
	author = "A. Mu\~noz and E. Ostua and M.~J. Bellido and A. Millan and J. Juan and D. Guerrero",
	title = "Building a SoC for industrial applications based on LEON microprocessor and a GNU/Linux distribution",
	booktitle = "Proc. 2008 IEEE International Symposium on Industrial Electronics (ISIE)",
	address = "Cambridge (United Kingdom)",
	month = "June",
	year = "2008",
	pages = "1727--1732", 
	isbn = "978­-1­-4244­-1666-­0"
};

@inproceedings{ostua08,
	author = "E. Ostua and J. Viejo and M.~J. Bellido and A. Millan and J. Juan and A. Mu\~noz",
	title = "Digital Data Processing Peripheral Design for an Embedded Application Based on the Microblaze Soft Core",
	booktitle = "Proc. 4th Southern Conference on Programmable Logic (SPL)",
	address = "San Carlos de Bariloche (Argentina)",
	month = "March",
	year = "2008",
	pages = "197--200", 
	isbn = "978-1-4244-1992-0"
};

@inproceedings{viejo08-1,
	author = "J. Viejo and A. Millan and M.~J. Bellido and E. Ostua and P. Ruiz-de-Clavijo and A. Mu\~noz",
	title = "Implementation of a FFT/IFFT module on FPGA: Comparison of methodologies",
	booktitle = "Proc. 4th Southern Conference on Programmable Logic (SPL)",
	address = "San Carlos de Bariloche (Argentina)",
	month = "March",
	year = "2008",
	pages = "7--11", 
	isbn = "978-1-4244-1992-0"
};

@inproceedings{viejo08-2,
	author = "J. Viejo and J. Juan and M.~J. Bellido and E. Ostua and A. Millan and P. Ruiz-­de-Clavijo and A. Mu\~noz and D. Guerrero",
	title = "Design and implementation of a SNTP client on FPGA",
	booktitle = "Proc. 2008 IEEE International Symposium on Industrial Electronics (ISIE)",
	address = "Cambridge (United Kingdom)",
	month = "June",
	year = "2008",
	pages = "1971--1975", 
	isbn = "978­-1­-4244­-1666-­0"
};

@inproceedings{villar08,
	author = "J.~I. Villar and M.~J. Bellido and E. Ostua and D. Guerrero and J. Juan and A. Mu\~noz",
	title = "Metodología de Diseño de SoC basada en OpenRisc sobre FPGA con Cores y Herramientas Libres",
	booktitle = "Proc. 8th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
	address = "Madrid (Spain)",
	month = "September",
	year = "2008",
	pages = "247--256", 
	isbn = "978-84-612-5635-8"
};

%%%% 2007 %%%%

@inproceedings{guerrero07-1,
	author = "D. Guerrero and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and A. Millan and E. Ostua and J. Viejo",
	title = "Síntesis lógica automatizada para esquemas de temporización de latches alternantes",
	booktitle = "Proc. 13th Iberchip Workshop (IWS)",
	address = "Lima (Peru)",
	month = "March",
	year = "2007",
	pages = "349--350", 
	isbn = "978-9972-242-09-0"
};

@inproceedings{guerrero07-2,
	author = "D. Guerrero and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and E. Ostua and J. Viejo",
	title = "Automatic logic synthesis for parallel alternating latches clocking schemes",
	booktitle = "Proc. Microtechnologies for the New Millennium 2007, SPIE",
	address = "Maspalomas (Spain)",
	month = "May",
	year = "2007",
	pages = "61--69", 
	isbn = "9780819467188"
};

@inproceedings{guerrero07-3,
	author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and E. Ostua and J. Viejo",
	title = "The effect of using separated bodies over static power consumption in Static Bulk-CMOS gates",
	booktitle = "Proc. 22th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Seville (Spain)",
	month = "November",
	year = "2007",
	pages = "181--185", 
	isbn = "978-84690-8629-2"
};

@inproceedings{munoz07,
	author = "A. Mu\~noz and E. Ostua and P. Ruiz-de-Clavijo and M.~J. Bellido and J. Viejo and A. Millan and J. Juan and D. Guerrero",
	title = "Un ejemplo de implantación de una distribución Linux en un SoC basado en hardware libre",
	booktitle = "Proc. 7th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
	address = "Zaragoza (Spain)",
	month = "September",
	year = "2007",
	pages = "85--92", 
	isbn = "978-84-9732-600-1"
};

@inproceedings{viejo07-1,
	author = "J. Viejo and A. Millan and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua and A. Mu\~noz",
	title = "Design of a FFT/IFFT module as an IP core suitable for embedded systems",
	booktitle = "Proc. 2nd IEEE International Symposium on Industrial Embedded Systems (SIES)",
	address = "Lisbon (Portugal)",
	month = "July",
	year = "2007",
	pages = "337--340", 
	isbn = "1-4244-0840-7"
};

@inproceedings{viejo07-2,
	author = "J. Viejo and A. Millan and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua and A. Mu\~noz",
	title = "Evaluación de metodologías para la implementación de un módulo FFT/IFFT sobre FPGA mediante herramientas a nivel de sistema",
	booktitle = "Proc. 7th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
	address = "Zaragoza (Spain)",
	month = "September",
	year = "2007",
	pages = "205--211", 
	isbn = "978-84-9732-600-1"
};

%%%% 2006 %%%%

@inproceedings{ostua06,
	author = "E. Ostua and J. Juan and J. Viejo and M.~J. Bellido and D. Guerrero and A. Millan and P. Ruiz-de-Clavijo",
	title = "A SOC design methodology for LEON2 on FPGA",
	booktitle = "Proc. 12th Iberchip Workshop (IWS)",
	address = "San Jose (Costa Rica)",
	month = "March",
	year = "2006",
	pages = "242--245"
};

@inproceedings{viejo06-1,
	author = "J. Viejo and E. Ostua and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and D. Guerrero",
	title = "Diseño e implementación óptima de periféricos de DSP con System Generator para MicroBlaze",
	booktitle = "Proc. 12th Iberchip Workshop (IWS)",
	address = "San Jose (Costa Rica)",
	month = "March",
	year = "2006",
	pages = "49--52"
};

@inproceedings{viejo06-2,
	author = "J. Viejo and M.~J. Bellido and A. Millan and E. Ostua and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero",
	title = "Efficient design and implementation on FPGA of a MicroBlaze peripheral for processing direct electrical networks measurements",
	booktitle = "Proc. 1st IEEE International Symposium on Industrial Embedded Systems (IES)",
	address = "Antibes Juan-Les-Pins (France)",
	month = "October",
	year = "2006",
	pages = "--", 
	isbn = "1-4244-0777-X"
};

@inproceedings{viejo06-3,
	author = "J. Viejo and M.~J. Bellido and A. Millan and E. Ostua and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero",
	title = "DSP peripheral on FPGA for electrical networks measurements",
	booktitle = "Proc. 21th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Barcelona (Spain)",
	month = "November",
	year = "2006",
	pages = "--", 
	isbn = "978-84-690-4144-4"
};

%%%% 2005 %%%%

@inproceedings{guerrero05-1,
	author = "D. Guerrero and M.~J. Bellido and J. Juan",
	title = "CMOS digital design techniques for low power and high speed",
	booktitle = "Proc. Conference on Design, Automation and Test in Europe (DATE)",
	address = "Munich (Germany)",
	month = "March",
	year = "2005",
	pages = "--", 
	isbn = "0-7695-2288-2"
};

@inproceedings{guerrero05-2,
	author = "D. Guerrero and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and E. Ostua and J. Viejo",
	title = "Algorithms to get the maximum operation frequency for skew-tolerant clocking schemes",
	booktitle = "Proc. Microtechnologies for the New Millennium 2005, SPIE",
	address = "Sevilla (Spain)",
	month = "May",
	year = "2005",
	pages = "467--478", 
	isbn = "9780819458322"
};

@inproceedings{millan05-1,
	author = "A. Millan and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua and J. Viejo",
	title = "Efficient design of a FFT/IFFT-64 module on ASIC",
	booktitle = "Proc. 11th Iberchip Workshop (IWS)",
	address = "Salvador de Bahia (Brazil)",
	month = "March",
	year = "2005",
	pages = "305--306", 
	isbn = "959-261-105-X"
};

@inproceedings{millan05-2,
	author = "A. Millan and M.~J. Bellido and J. Juan",
	title = "Optimization techniques for dynamic behavior modeling of digital CMOS VLSI circuits in nanometric technologies",
	booktitle = "Proc. PhD Research In Micro-Electronics and Electronics (PRIME)",
	address = "Lausanne (Switzerland)",
	month = "July",
	year = "2005",
	pages = "374--377", 
	isbn = "0-78039345-7"
};

@inproceedings{millan05-3,
	author = "A. Millan and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua and J. Viejo",
	title = "Analysis of internal power consumption in SCMOS gates in submicronic/nanometric technologies",
	booktitle = "Proc. 20th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Lisboa (Portugal)",
	month = "November",
	year = "2005",
	pages = "--", 
	isbn = "972-99387-2-5"
};

@inproceedings{ostua05,
	author = "E. Ostua and J. Viejo and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and D. Guerrero",
	title = "Entorno de desarrollo para SOC basado en el microprocesador LEON2",
	booktitle = "Proc. 11th Iberchip Workshop (IWS)",
	address = "Salvador de Bahia (Brazil)",
	month = "March",
	year = "2005",
	pages = "429--430", 
	isbn = "959-261-105-X"
};

@inproceedings{clavijo05,
	author = "P. Ruiz-de-Clavijo and M.~J. Bellido and J. Juan",
	title = "HALOTIS - High accurate logic timing simulator",
	booktitle = "Proc. PhD Research In Micro-Electronics and Electronics (PRIME)",
	address = "Lausanne (Switzerland)",
	month = "July",
	year = "2005",
	pages = "191--194", 
	isbn = "0-78039345-7"
};

@inproceedings{viejo05-1,
	author = "J. Viejo and E. Ostua and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and D. Guerrero",
	title = "Diseño, implementacion y aplicacion a SOC del microprocesador Picoblaze",
	booktitle = "Proc. 11th Iberchip Workshop (IWS)",
	address = "Salvador de Bahia (Brazil)",
	month = "March",
	year = "2005",
	pages = "431--432", 
	isbn = "959-261-105-X"
};

%%%% 2004 %%%%

@inproceedings{guerrero04,
	author = "D. Guerrero and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and E. Ostua",
	title = "Four phase alternating latches clocking scheme for CMOS sequential circuits",
	booktitle = "Proc. 19th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Bordeaux (France)",
	month = "November",
	year = "2004",
	pages = "780--783", 
	isbn = "2-9522971-0-X"
};

%%%% 2003 %%%%

@inproceedings{guerrero03,
	author = "D. Guerrero and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and G. Wilke and J.~L. Güntzel",
	title = "Estimation of floating cube delay using transistor path computational delay models for CMOS circuits",
	booktitle = "Proc. 18th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Ciudad Real (Spain)",
	month = "November",
	year = "2003",
	pages = "95--99", 
	isbn = "84-87087-40-X"
};

@inproceedings{millan03-1,
	author = "A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua",
	title = "Using sampled input signals for SCMOS gates characterization",
	booktitle = "Proc. 18th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Ciudad Real (Spain)",
	month = "November",
	year = "2003",
	pages = "275--280", 
	isbn = "84-87087-40-X"
};

@inproceedings{millan03-2,
	author = "A. Millan and M.~J. Bellido and J. Juan and D. Guerrero and P. Ruiz-de-Clavijo and E. Ostua",
	title = "Internode: Internal node logic computational model",
	booktitle = "Proc. 36th Annual Simulation Symposium (Advanced Simulation Technologies Conference, ASTC)",
	address = "Orlando, FL (United States of America)",
	month = "March",
	year = "2003",
	pages = "241--248", 
	isbn = "0-7695-1911-3"
};

@inproceedings{millan03-3,
	author = "A. Millan and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua",
	title = "Diseño eficiente de un módulo FFT/IFFT-64 sobre FPGA",
	booktitle = "Proc. 3rd Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
	address = "Madrid (Spain)",
	month = "September",
	year = "2003",
	pages = "107--114", 
	isbn = "84-600-9928-8"
};

@inproceedings{ostua03-1,
	author = "E. Ostua and M.~J. Bellido and P. Ruiz-de-Clavijo and A. Barriga and A. Millan and D. Guerrero and J. Juan",
	title = "Diseño e implementación sobre FPGA de un microprocesador empotrable en SOC de control",
	booktitle = "Proc. 3rd Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
	address = "Madrid (Spain)",
	month = "September",
	year = "2003",
	pages = "385--392", 
	isbn = "84-600-9928-8"
};

@inproceedings{ostua03-2,
	author = "E. Ostua and M.~J. Bellido and A. Barriga and P. Ruiz-de-Clavijo and J. Juan and A. Millan and D. Guerrero",
	title = "Diseño e implementación sobre FPGA de un microprocesador empotrable en SOC de Control",
	booktitle = "Proc. Seminario Anual de Automática, Electrónica Industrial e Instrumentación (SAAEI, Annual Seminar on Automatic Control, Industrial Electronics and Instrumentation)",
	address = "Vigo (Spain)",
	month = "September",
	year = "2003",
	pages = "--", 
	isbn = "84-688-3055-6"
};

@inproceedings{clavijo03,
	author = "P. Ruiz-de-Clavijo and J. Juan and J.~R. Fernandes and M.~J. Bellido and A. Millan and D. Guerrero",
	title = "Delay degradation effect in current balanced logic cells",
	booktitle = "Proc. 18th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Ciudad Real (Spain)",
	month = "November",
	year = "2003",
	pages = "163--165", 
	isbn = "84-87087-40-X"
};

%%%% 2002 %%%%

@inproceedings{estevez02,
	author = "M. Estevez and M.~J. Bellido and C.~J. Jimenez and J. Juan",
	title = "Design of a Microprocessor for SOC applications",
	booktitle = "Proc. 4th European Workshop on Microelectronics Education (EWME)",
	address = "Vigo (Spain)",
	month = "May",
	year = "2002",
	pages = "149--152", 
	isbn = "84-267-1325-4"
};

@inproceedings{guerrero02,
	author = "D. Guerrero and M.~J. Bellido and J. Juan and P. Paulino and A. Millan",
	title = "Two phase alternating latches clocking scheme for CMOS sequential circuits",
	booktitle = "Proc. 17th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Santander (Spain)",
	month = "November",
	year = "2002",
	pages = "159--162"
};

@inproceedings{millan02,
	author = "A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and D. Guerrero",
	title = "Integration of a characterization method for normal propagation delay into AUTODDM",
	booktitle = "Proc. 17th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Santander (Spain)",
	month = "November",
	year = "2002",
	pages = "93--97"
};

%%%% 2001 %%%%

@inproceedings{baena01,
	author = "C. Baena and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and C.~J. Jimenez and M. Valencia",
	title = "Simulation-driven switching activity evaluation of CMOS digital circuits",
	booktitle = "Proc. 16th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Porto (Portugal)",
	month = "November",
	year = "2001",
	pages = "608--612"
};

@inproceedings{bellido01,
	author = "M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and A.~J. Acosta and M. Valencia",
	title = "Gate-level simulation of CMOS circuits using the IDDM model",
	booktitle = "Proc. IEEE International Symposium on Circuits and Systems (ISCAS)",
	address = "Darling Harbour, Sydney (Australia)",
	month = "May",
	year = "2001",
	pages = "483--486", 
	isbn = "0-7803-6687-5"
};

@inproceedings{juan01-1,
	author = "J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and C. Baena and M. Valencia",
	title = "AUTODDM: AUTOmatic characterization tool for the Delay Degradation Model",
	booktitle = "Proc. International Conference on Electronics, Circuits and Systems (ICECS)",
	address = "Malta",
	month = "September",
	year = "2001",
	pages = "1631--1634", 
	isbn = "0-7803-7057-0"
};

@inproceedings{juan01-2,
	author = "J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and C. Baena and M. Valencia",
	title = "DDM characterization methodology and automation",
	booktitle = "Proc. 11th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)",
	address = "Yverdon-Les-Bains (Switzerland)",
	month = "September",
	year = "2001",
	pages = "5.2.1--5.2.10"
};

@inproceedings{juan01-3,
	author = "J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and C.~J. Jimenez and C. Baena and M. Valencia",
	title = "Logic-timing simulation using the Degradation Delay Model",
	booktitle = "Proc. International Workshop on Logic and Synthesis (IWLS)",
	address = "Granlibakken, CA (United States of America)",
	month = "June",
	year = "2001",
	pages = "237--242"
};

@inproceedings{clavijo01-1,
	author = "P. Ruiz-de-Clavijo and M.~J. Bellido and J. Juan and C. Baena",
	title = "ISS: Interactive Simulation System",
	booktitle = "Proc. 16th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Porto (Portugal)",
	month = "November",
	year = "2001",
	pages = "410--413"
};

@inproceedings{clavijo01-2,
	author = "P. Ruiz-de-Clavijo and J. Juan and M.~J. Bellido and A.~J. Acosta and M. Valencia",
	title = "HALOTIS: High Accuracy LOgic TIming Simulator with inertial and degradation delay model",
	booktitle = "Proc. Conference on Design, Automation and Test in Europe (DATE)",
	address = "Munich (Germany)",
	month = "March",
	year = "2001",
	pages = "467--471", 
	isbn = "0-7695-0993-2"
};

%%%% 2000 %%%%

@inproceedings{juan00-1,
	author = "J. Juan and P. Ruiz-de-Clavijo and M.~J. Bellido and A.~J. Acosta and M. Valencia",
	title = "Inertial and Degradation Delay Model for CMOS Logic Gates",
	booktitle = "Proc. IEEE International Symposium on Circuits and Systems (ISCAS)",
	address = "Geneva (Switzerland)",
	month = "May",
	year = "2000",
	pages = "459--462", 
	isbn = "0-7803-5485-0"
};

@inproceedings{juan00-2,
	author = "J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and A.~J. Acosta and M. Valencia",
	title = "Gate-Level Modeling of the Delay Degradation Effect",
	booktitle = "Proc. 15th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Montpellier - Le Corum (France)",
	month = "November",
	year = "2000",
	pages = "537--542"
};

%%%% Teaching Conferences %%%%

%%%% 2012 %%%%

@inproceedings{juan12,
	author = "J. Juan and E. Ostua and D. Guerrero",
	title = "Experiencia de renovación metodológica en la enseñanza de la electrónica digital básica",
	booktitle = "Proc. 10th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)",
	address = "Vigo (Spain)",
	month = "June",
	year = "2012",
	pages = "52--57", 
	isbn = "978-84-8158-570-4"
};

@inproceedings{ruiz12,
	author = "J. Ruiz and D. Guerrero and I. Gomez and J. Viejo",
	title = "Implementación de un procesador académico simple así como de un entorno de programación y depuración para el mismo",
	booktitle = "Proc. 10th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)",
	address = "Vigo (Spain)",
	month = "June",
	year = "2012",
	pages = "58--63", 
	isbn = "978-84-8158-570-4"
};

%%%% 2008 %%%%

@inproceedings{munoz08-1,
	author = "A. Mu\~noz and A. Millan and P. Ruiz-de-Clavijo and J. Viejo and E. Ostua and D. Guerrero",
	title = "Desarrollo de una interfaz RS-232 para el manejo de un coche de radiocontrol desde el PC",
	booktitle = "Proc. 8th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)",
	address = "Zaragoza (Spain)",
	month = "July",
	year = "2008",
	pages = "119", 
	isbn = "978-84-7733-628-0"
};

@inproceedings{munoz08-2,
	author = "A. Mu\~noz, E. Ostua, M.~J. Bellido, P. Ruiz-de-Clavijo, J.~I. Villar, J. Quiros",
	title = "Ampliación de periféricos para aplicaciones embebidas basadas en hardware y software libre",
	booktitle = "Proc. 5th International Conference on Telecommunications, Electronics and Control (TELEC)",
	address = "Santiago de Cuba (Cuba)",
	month = "July",
	year = "2008",
	pages = "--", 
	isbn = "978-84-00-08680-0"
};

@inproceedings{viejo08-1,
	author = "J. Viejo and E. Ostua and M.~J. Bellido and J. Juan and D. Guerrero and A. Mu\~noz",
	title = "La primera experiencia en el diseño de sistemas digitales sobre FPGAs",
	booktitle = "Proc. 8th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)",
	address = "Zaragoza (Spain)",
	month = "July",
	year = "2008",
	pages = "161", 
	isbn = "978-84-7733-628-0"
};

@inproceedings{viejo08-2,
	author = "J. Viejo and E. Ostua and M.~J. Bellido and P. Ruiz-de-Clavijo and A. Mu\~noz and A. Millan",
	title = "Aplicación de Picoblaze al diseño de sistemas de control industrial",
	booktitle = "Proc. 5th International Conference on Telecommunications, Electronics and Control (TELEC)",
	address = "Santiago de Cuba (Cuba)",
	month = "July",
	year = "2008",
	pages = "--", 
	isbn = "978-84-00-08680-0"
};

@inproceedings{villar08,
	author = "J.~I. Villar and M.~J. Bellido and E. Ostua and D. Guerrero and J. Juan and A. Mu\~noz",
	title = "Metodología de diseño SOC con OpenRISC sobre FPGA",
	booktitle = "Proc. 5th International Conference on Telecommunications, Electronics and Control (TELEC)",
	address = "Santiago de Cuba (Cuba)",
	month = "July",
	year = "2008",
	pages = "--", 
	isbn = "978-84-00-08680-0"
};

%%%% 2006 %%%%

@inproceedings{alvarez06,
	author = "A. Alvarez and A. Millan and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua and J. Viejo",
	title = "Desarrollo en VHDL de un filtro digital genérico basado en estructuras canónicas",
	booktitle = "Proc. 7th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)",
	address = "Madrid (Spain)",
	month = "July",
	year = "2006",
	pages = "285--286", 
	isbn = "84-689-9590-8"
};

@inproceedings{jimenez06,
	author = "C.~J. Jimenez and C. Baena and E. Ostua and M. Valencia",
	title = "Introducción de dispositivos programables en prácticas de laboratorio",
	booktitle = "Proc. 7th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)",
	address = "Madrid (Spain)",
	month = "July",
	year = "2006",
	pages = "135--136", 
	isbn = "84-689-9590-8"
};

@inproceedings{viejo06,
	author = "J. Viejo and E. Ostua and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and D. Guerrero",
	title = "Diseño e implementación de SOPC basados en el microprocesador PicoBlaze",
	booktitle = "Proc. 7th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)",
	address = "Madrid (Spain)",
	month = "July",
	year = "2006",
	pages = "319--320", 
	isbn = "84-689-9590-8"
};

%%%% 2004 %%%%

@inproceedings{franco04-1,
	author = "E. Franco and F. Montero and E. Ostua and M.~J. Bellido and P. Ruiz-de-Clavijo and A. Millan and D. Guerrero and J. Juan",
	title = "Diseño del microcontrolador 8051 con modulo ensamblador-generador de ROM en lenguaje VHDL",
	booktitle = "Proc. 6th Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE)",
	address = "Valencia (Spain)",
	month = "July",
	year = "2004",
	pages = "--", 
	isbn = "84-688-7339-X"
};

@inproceedings{franco04-2,
	author = "E. Franco and F. Montero and E. Ostua and M.~J. Bellido and P. Ruiz-de-Clavijo and A. Millan and D. Guerrero and J. Juan",
	title = "Microcontrolador 8051: compilador de ROM y diseño del micro en VHDL",
	booktitle = "Proc. 3rd International Conference on Telecommunications, Electronics and Control (TELEC)",
	address = "Santiago de Cuba (Cuba)",
	month = "July",
	year = "2004",
	pages = "--", 
	isbn = "84-8138-607-3"
};

@inproceedings{guerrero04,
	author = "D. Guerrero and E. Ostua and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and J.~I. Villar",
	title = "Análisis del comportamiento de la videoconsola Atari 2600 como sistema digital real basado en microprocesador en el laboratorio de Electronica",
	booktitle = "Proc. 6th Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE)",
	address = "Valencia (Spain)",
	month = "July",
	year = "2004",
	pages = "--", 
	isbn = "84-688-7339-X"
};

@inproceedings{jurado04-1,
	author = "P. Jurado and J. Juan and P. Ruiz-de-Clavijo and M.~J. Bellido and A. Millan and D. Guerrero and E. Ostua",
	title = "ADKI: un sistema web de adquisicion de datos bajo Linux",
	booktitle = "Proc. 6th Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE)",
	address = "Valencia (Spain)",
	month = "July",
	year = "2004",
	pages = "--", 
	isbn = "84-688-7339-X"
};

@inproceedings{jurado04-2,
	author = "P. Jurado and J. Juan and P. Ruiz-de-Clavijo and M.~J. Bellido and A. Millan and D. Guerrero and E. Ostua",
	title = "Un sistema web para la adquisición de datos y control basado en GNU/Linux",
	booktitle = "Proc. 3rd International Conference on Telecommunications, Electronics and Control (TELEC)",
	address = "Santiago de Cuba (Cuba)",
	month = "July",
	year = "2004",
	pages = "--", 
	isbn = "84-8138-607-3"
};

@inproceedings{nunez04,
	author = "J.~L. Nuñez and A. Millan and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua and M.~J. Bellido and J. Juan",
	title = "Seguridad en Internet: Web Spoofing",
	booktitle = "Proc. 6th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)",
	address = "Valencia (Spain)",
	month = "July",
	year = "2004",
	pages = "--", 
	isbn = "84-688-7339-X"
};

%%%% 2002 %%%%

@inproceedings{castro02,
	author = "J. Castro and A. Millan and P. Ruiz-de-Clavijo",
	title = "Sistema de control de grupos de prácticas: aplicación al ámbito docente del Departamento de Tecnología Electrónica de la Universidad de Sevilla",
	booktitle = "Proc. 5th Congreso sobre Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE)",
	address = "Las Palmas de Gran Canaria (Spain)",
	month = "February",
	year = "2002",
	pages = "503--506"};

@inproceedings{estevez02,
	author = "M. Estevez and M.~J. Bellido and C.~J. Jimenez and J. Juan",
	title = "Design of a microprocessor for SOC applications",
	booktitle = "Proc. 2nd Conferencia Internacional sobre Telecomunicación, Electrónica y Control (TELEC)",
	address = "Santiago de Cuba (Cuba)",
	month = "July",
	year = "2002",
	pages = "--", 
	isbn = "84-8138-506-9"
};

%%%% 2000 %%%%

@inproceedings{bellido00-1,
	author = "M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and A. Barriga",
	title = "Aplicación de ALLIANCE al diseño de Circuitos Digitales VLSI",
	booktitle = "Proc. 1st Conferencia Internacional sobre Telecomunicación, Electrónica y Control (TELEC)",
	address = "Santiago de Cuba (Cuba)",
	month = "July",
	year = "2000",
	pages = "--", 
	isbn = "84-8138-393-7"
};

@inproceedings{bellido00-2,
	author = "M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and A.~J. Acosta",
	title = "Concepción de un microprocesador: de la especificación a la realización",
	booktitle = "Proc. 4th Congreso sobre Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE)",
	address = "Barcelona (Spain)",
	month = "September",
	year = "2000",
	pages = "565--568", 
	isbn = "84-600-9596-7"
};


%%%% Tesis %%%%

@PHDTHESIS{juan00,
   author = "Juan, J.",
   title = "Degradación del retraso de propagación en puertas lógicas CMOS VLSI",
   school = "Escuela Técnica Superior de Ingeniería Informática, Sevilla, Espa\~na",
   year = "2000"
   };

@PHDTHESIS{ruiz07,
   author = "Ruiz-de-Clavijo, P.",
   title = "Simulación lógica temporal de altas prestaciones y aplicación a la estimación del consumo de potencia y corriente en circuitos integrados CMOS-VLSI",
   school = "Escuela Técnica Superior de Ingeniería Informática, Sevilla, Espa\~na",
   year = "2007"
   };

@PHDTHESIS{millan08,
   author = "Millan, A.",
   title = "Técnicas de optimización para el modelado y la caracterización del comportamiento dinámico de circuitos digitales CMOS en tecnologías UDSM",
   school = "Escuela Técnica Superior de Ingeniería Informática, Sevilla, Espa\~na",
   year = "2008"
   };

@PHDTHESIS{viejo11,
   author = "Viejo, J.",
   title = "Dise\~no e implementación sobre FPGA de sistemas digitales de bajo coste para la sincronización de equipos sobre redes de comunicación usando el protocolo SNTP",
   school = "Escuela Técnica Superior de Ingeniería Informática, Sevilla, Espa\~na",
   year = "2011"
   };