%%%% 2018 %%%%
@inproceedings{cano18,
author = "G. Cano-Quiveu",
title = "OpenRISC hardware bootloader over WiFi",
booktitle = "The open source digital design conference (ORConf)",
address = "Gdansk (Poland)",
month = "September",
year = "2018",
pages = ""
};
%%%% Conferences %%%%
%%%% 2016 %%%%
@inproceedings{fayula16,
author = "M. Fayula and J. Juan and J. Viejo",
title = "Case study: performance and power analysis of a dynamically reconfigurable hardware/software cryptosystem",
booktitle = "Proc. 22th Iberchip Workshop (IWS)",
address = "Florianopolis (Brazil)",
month = "February",
year = "2016",
pages = "112--115"
};
@inproceedings{millan16,
author = "A. Millan and J. Viejo and J. Quiros and M. J. Bellido and D. Guerrero and E. Ostua",
title = "Building a basic membrane computer",
booktitle = "Proc. 14th Brainstorming Week on Membrane Computing (BWMC)",
address = "Universidad de Sevilla, Sevilla (Spain)",
month = "February",
year = "2016",
pages = "269--280"
};
%%%% 2015 %%%%
@INPROCEEDINGS{7365121,
author = {J. I. Villar and J. Juan and D. Guerrero and M. J. Bellido and J. Viejo},
booktitle = {Electronic System Level Synthesis Conference (ESLsyn), 2015},
title = {evercodeML: A formal language for SoC integration},
year = 2015,
pages = {23-26},
abstract = {Complex SoC design devote a great part of the developing time to module integration tasks. The necessity of automating system integration at high-level has yield to the development of module description languages like IP-XACT. However, the available options today still lack advanced parametrization capabilities needed to design complex systems with very heterogeneous IP-cores and module providers. This contribution introduces a formal language for SoC integration that overcomes these limitations.},
keywords = {formal languages;logic design;system-on-chip;IP-XACT;SoC integration;complex SoC design;evercodeML;formal language;heterogeneous IP-cores;module description languages;module providers;system integration;Field programmable gate arrays;Generators;Hardware;Hardware design languages;Packaging;System integration;XML;FPGA;IP-XACT;IP-core;SoC},
issn = {2117-4628},
isbn = {979-10-92279-13-9},
url = {http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7365121},
month = {June}
};
%%%% 2013 %%%%
@inproceedings{villar13,
author = "J.~I. Villar and J. Juan and M.~J. Bellido and J. Viejo",
title = "XML-based Description Language for Heterogeneous and Highly-configurable IP-core Integration",
booktitle = "Proc. 19th Iberchip Workshop (IWS)",
address = "Cusco (Peru)",
month = "February",
year = 2013,
pages = "--",
isbn = "978-1-4673-4899-7"
};
@inproceedings{juan13,
author = "J. Juan and J. Viejo and M.~J. Bellido",
title = {Network Time Synchronization: A Full Hardware Approach},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation},
series = {Lecture Notes in Computer Science},
volume = {7606},
year = 2013,
pages = {225-234},
publisher = {Springer Berlin Heidelberg},
isbn = {978-3-642-36156-2},
doi = {10.1007/978-3-642-36157-9_23},
editor = {Ayala, JoséL. and Shang, Delong and Yakovlev, Alex},
url = {http://dx.doi.org/10.1007/978-3-642-36157-9_23},
keywords = {digital systems; hardware; network time synchronization; FPGA}
}
@inproceedings{verlan13,
author = "S. Verlan and J. Quiros",
title = "Fast Hardware Implementations of P Systems",
booktitle = "Membrane Computing",
series = {Lecture Notes in Computer Science},
volume={7762},
year = "2013",
pages = {404-423},
publisher={Springer Berlin Heidelberg},
isbn={978-3-642-36750-2},
doi={10.1007/978-3-642-36751-9_27},
editor={Csuhaj-Varjú, Erzsébet and Gheorghe, Marian and Rozenberg, Grzegorz and Salomaa, Arto and Vaszil, György},
url={http://dx.doi.org/10.1007/978-3-642-36751-9_27}
};
%%%% 2012 %%%%
@inproceedings{ruiz12,
author = "J. Ruiz and J.~I. Villar and M.~J. Bellido and D. Guerrero and J. Viejo and P. Ruiz-de-Clavijo and J. Juan",
title = "Diseño e implementación de un controlador domótico reconfigurable basado en hardware y software libre",
booktitle = "Proc. 12th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
address = "Elche (Spain)",
month = "September",
year = "2012",
pages = "161--166",
isbn = "978-84-695-4470-9"
};
%%%% 2011 %%%%
@inproceedings{quiros11,
author = "J. Quiros and J. Viejo and A. Millan and A. Mu\~noz and J.~I. Villar and D. Guerrero",
title = "Implementation of a configuration server for a hardware SNTP synchronization platform based on FPGA",
booktitle = "Proc. 7th Southern Conference on Programmable Logic (SPL)",
address = "Cordoba (Argentina)",
month = "April",
year = "2011",
pages = "239--244",
isbn = "978-1-4244-8846-9"
};
@inproceedings{villar11,
author = "J.~I. Villar and J. Juan and M.~J. Bellido and J. Viejo and D. Guerrero and J. Decaluwe",
title = "Python as a Hardware Description Language: A Case Study",
booktitle = "Proc. 7th Southern Conference on Programmable Logic (SPL)",
address = "Cordoba (Argentina)",
month = "April",
year = "2011",
pages = "117--122",
isbn = "978-1-4244-8846-9"
};
%%%% 2010 %%%%
@inproceedings{quiros10,
author = "J. Quiros and J. Viejo and A. Mu\~noz and A. Millan and E. Ostua and J.~I. Villar",
title = "Implementación sobre FPGA de un cliente SNTP usando MicroBlaze",
booktitle = "Proc. 16th Iberchip Workshop (IWS)",
address = "Iguazu Falls (Brazil)",
month = "February",
year = "2010",
pages = "--"
};
@inproceedings{viejo10-1,
author = "J. Viejo and J.~I. Villar and J. Juan and A. Millan and M.~J. Bellido and E. Ostua",
title = "Design and implementation of a suitable core for on-chip long-term verification",
booktitle = "Proc. 5th IEEE International Symposium on Industrial Embedded Systems (SIES)",
address = "Trento (Italy)",
month = "July",
year = "2010",
pages = "234--237",
isbn = "978-1-4244-5840-0"
};
@inproceedings{viejo10-2,
author = "J. Viejo and J.~I. Villar and J. Juan and A. Millan and M.~J. Bellido and J. Quiros",
title = "Verificación on-chip de larga duración de sistemas con eventos lógicos dispersos en el tiempo",
booktitle = "Proc. 10th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
address = "Valencia (Spain)",
month = "September",
year = "2010",
pages = "269--276",
isbn = "978-84-92812-56-1"
};
@inproceedings{viejo10-3,
author = "J. Viejo and J.~I. Villar and J. Juan and A. Millan and E. Ostua and J. Quiros",
title = "Long-term on-chip verification of systems with logical events scattered in time",
booktitle = "Proc. 25th Conference on Design of Circuits and Integrated Systems (DCIS)",
address = "Lanzarote (Spain)",
month = "November",
year = "2010",
pages = "323--326",
isbn = "978-84-693-7393-4"
};
%%%% 2009 %%%%
@inproceedings{guerrero09-1,
author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and E. Ostua",
title = "Performance Analysis of Bulk-CMOS Gates Using Separated Wells",
booktitle = "Proc. 15th Iberchip Workshop (IWS)",
address = "Buenos Aires (Argentina)",
month = "March",
year = "2009",
pages = "54--59"
};
@inproceedings{guerrero09-2,
author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and E. Ostua",
title = "Delay and Power Consumption of Static Bulk-CMOS Gates Using Independent Bodies",
booktitle = "Proc. 4th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)",
address = "Cairo (Egypt)",
month = "April",
year = "2009",
pages = "191--196",
isbn = "978-1-4244-4321-5"
};
@inproceedings{millan09,
author = "A. Millan and J. Juan and M.~J. Bellido and D. Guerrero and P. Ruiz-de-Clavijo and J. Viejo",
title = "Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates",
booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
series = "Lecture Notes in Computer Science",
volume = "5349",
month = "September",
year = "2009",
pages = "389--398",
publisher = "Springer Berlin Heidelberg",
isbn = "978-3-540-95947-2",
doi = "10.1007/978-3-540-95948-9_39"
}
@inproceedings{ostua09,
author = "E. Ostua and M.~J. Bellido and J. Viejo and A. Millan and A. Mu\~noz and D. Guerrero",
title = "Aplicación de Picoblaze como Emulador/Receptor de un GPS en el diseño hardware de un cliente/servidor SNTP",
booktitle = "Proc. 9th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
address = "Madrid (Spain)",
month = "September",
year = "2009",
pages = "193--202",
isbn = "978-84-8138-832-9"
};
@inproceedings{viejo09-1,
author = "J. Viejo and J. Juan and E. Ostua and M.~J. Bellido and A. Millan and A. Mu\~noz and J.~I. Villar",
title = "Accurate and compact implementation of a hardware SNTP Client",
booktitle = "Proc. 15th Iberchip Workshop (IWS)",
address = "Buenos Aires (Argentina)",
month = "March",
year = "2009",
pages = "504--509"
};
@inproceedings{viejo09-2,
author = "J. Viejo and J. Juan and E. Ostua and A. Millan and P. Ruiz-de-Clavijo and J.~I. Villar and J. Quiros",
title = "Implementación sobre FPGA de un cliente SNTP de bajo coste y alta precisión",
booktitle = "Proc. 9th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
address = "Madrid (Spain)",
month = "September",
year = "2009",
pages = "359--366",
isbn = "978-84-8138-832-9"
};
@inproceedings{villar09-1,
author = "J.~I. Villar and J. Juan and M.~J. Bellido",
title = "Efficient techniques and methodologies for embedded system design using free hardware and open standards",
booktitle = "Proc. 19th International Conference on Field Programmable Logic and Applications (FPL)",
address = "Prague (Czech Republic)",
month = "August",
year = "2009",
pages = "719--720",
isbn = "978-1-4244-3892-1"
};
@inproceedings{villar09-2,
author = "J.~I. Villar and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and D.Guerrero and A. Mu\~noz",
title = "Usando Python como HDL: Estudio comparativo de resultados basado en el desarrollo de un periférico real",
booktitle = "Proc. 9th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
address = "Madrid (Spain)",
month = "September",
year = "2009",
pages = "33--42",
isbn = "978-84-8138-832-9"
};
%%%% 2008 %%%%
@inproceedings{guerrero08-1,
author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and J. Viejo and A. Mu\~noz",
title = "Using Independent Bodies in Bulk-CMOS Gates",
booktitle = "Proc. 11th IEEE Symposium on Low-Power and High-Speed Chips (COOLChips)",
address = "Yokohama (Japan)",
month = "April",
year = "2008",
pages = "221"
};
@inproceedings{guerrero08-2,
author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo, E.Ostua",
title = "Delay and Power Consumption of Static Bulk-CMOS Gates Using Independent Bodies",
booktitle = "Proc. 7th Journées d'études Faible Tension Faible Consommation (FTFC)",
address = "Louvain-la-Neuve (Belgium)",
month = "May",
year = "2008",
pages = "105--110"
};
@inproceedings{millan08,
author = "A. Millan and M.~J. Bellido and J. Juan and D. Guerrero and P. Ruiz-de-Clavijo and J. Viejo",
title = "Internal Power Dissipation of Static CMOS Gates in UDSM Technologies",
booktitle = "Proc. 11th IEEE Symposium on Low-Power and High-Speed Chips (COOLChips)",
address = "Yokohama (Japan)",
month = "April",
year = "2008",
pages = "127"
};
@inproceedings{munoz08,
author = "A. Mu\~noz and E. Ostua and M.~J. Bellido and A. Millan and J. Juan and D. Guerrero",
title = "Building a SoC for industrial applications based on LEON microprocessor and a GNU/Linux distribution",
booktitle = "Proc. 2008 IEEE International Symposium on Industrial Electronics (ISIE)",
address = "Cambridge (United Kingdom)",
month = "June",
year = "2008",
pages = "1727--1732",
isbn = "978-1-4244-1666-0"
};
@inproceedings{ostua08,
author = "E. Ostua and J. Viejo and M.~J. Bellido and A. Millan and J. Juan and A. Mu\~noz",
title = "Digital Data Processing Peripheral Design for an Embedded Application Based on the Microblaze Soft Core",
booktitle = "Proc. 4th Southern Conference on Programmable Logic (SPL)",
address = "San Carlos de Bariloche (Argentina)",
month = "March",
year = "2008",
pages = "197--200",
isbn = "978-1-4244-1992-0"
};
@inproceedings{viejo08-1,
author = "J. Viejo and A. Millan and M.~J. Bellido and E. Ostua and P. Ruiz-de-Clavijo and A. Mu\~noz",
title = "Implementation of a FFT/IFFT module on FPGA: Comparison of methodologies",
booktitle = "Proc. 4th Southern Conference on Programmable Logic (SPL)",
address = "San Carlos de Bariloche (Argentina)",
month = "March",
year = "2008",
pages = "7--11",
isbn = "978-1-4244-1992-0"
};
@inproceedings{viejo08-2,
author = "J. Viejo and J. Juan and M.~J. Bellido and E. Ostua and A. Millan and P. Ruiz-de-Clavijo and A. Mu\~noz and D. Guerrero",
title = "Design and implementation of a SNTP client on FPGA",
booktitle = "Proc. 2008 IEEE International Symposium on Industrial Electronics (ISIE)",
address = "Cambridge (United Kingdom)",
month = "June",
year = "2008",
pages = "1971--1975",
isbn = "978-1-4244-1666-0"
};
@inproceedings{villar08,
author = "J.~I. Villar and M.~J. Bellido and E. Ostua and D. Guerrero and J. Juan and A. Mu\~noz",
title = "Metodología de Diseño de SoC basada en OpenRisc sobre FPGA con Cores y Herramientas Libres",
booktitle = "Proc. 8th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
address = "Madrid (Spain)",
month = "September",
year = "2008",
pages = "247--256",
isbn = "978-84-612-5635-8"
};
%%%% 2007 %%%%
@inproceedings{guerrero07-1,
author = "D. Guerrero and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and A. Millan and E. Ostua and J. Viejo",
title = "Síntesis lógica automatizada para esquemas de temporización de latches alternantes",
booktitle = "Proc. 13th Iberchip Workshop (IWS)",
address = "Lima (Peru)",
month = "March",
year = "2007",
pages = "349--350",
isbn = "978-9972-242-09-0"
};
@inproceedings{guerrero07-2,
author = "D. Guerrero and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and E. Ostua and J. Viejo",
title = "Automatic logic synthesis for parallel alternating latches clocking schemes",
booktitle = "Proc. Microtechnologies for the New Millennium 2007, SPIE",
address = "Maspalomas (Spain)",
month = "May",
year = "2007",
pages = "61--69",
isbn = "9780819467188"
};
@inproceedings{guerrero07-3,
author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and E. Ostua and J. Viejo",
title = "Static power consumption in CMOS gates using independent bodies",
booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
series = "Lecture Notes in Computer Science",
volume = "4644",
month = "September",
year = "2007",
pages = "404--412",
publisher = "Springer Berlin Heidelberg",
isbn = "978-3-540-74441-2",
doi = "10.1007/978-3-540-74442-9_39"
}
@inproceedings{guerrero07-4,
author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and E. Ostua and J. Viejo",
title = "The effect of using separated bodies over static power consumption in Static Bulk-CMOS gates",
booktitle = "Proc. 22th Conference on Design of Circuits and Integrated Systems (DCIS)",
address = "Seville (Spain)",
month = "November",
year = "2007",
pages = "181--185",
isbn = "978-84690-8629-2"
};
@inproceedings{munoz07,
author = "A. Mu\~noz and E. Ostua and P. Ruiz-de-Clavijo and M.~J. Bellido and J. Viejo and A. Millan and J. Juan and D. Guerrero",
title = "Un ejemplo de implantación de una distribución Linux en un SoC basado en hardware libre",
booktitle = "Proc. 7th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
address = "Zaragoza (Spain)",
month = "September",
year = "2007",
pages = "85--92",
isbn = "978-84-9732-600-1"
};
@inproceedings{viejo07-1,
author = "J. Viejo and A. Millan and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua and A. Mu\~noz",
title = "Design of a FFT/IFFT module as an IP core suitable for embedded systems",
booktitle = "Proc. 2nd IEEE International Symposium on Industrial Embedded Systems (SIES)",
address = "Lisbon (Portugal)",
month = "July",
year = "2007",
pages = "337--340",
isbn = "1-4244-0840-7"
};
@inproceedings{viejo07-2,
author = "J. Viejo and A. Millan and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua and A. Mu\~noz",
title = "Evaluación de metodologías para la implementación de un módulo FFT/IFFT sobre FPGA mediante herramientas a nivel de sistema",
booktitle = "Proc. 7th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
address = "Zaragoza (Spain)",
month = "September",
year = "2007",
pages = "205--211",
isbn = "978-84-9732-600-1"
};
%%%% 2006 %%%%
@inproceedings{ostua06,
author = "E. Ostua and J. Juan and J. Viejo and M.~J. Bellido and D. Guerrero and A. Millan and P. Ruiz-de-Clavijo",
title = "A SOC design methodology for LEON2 on FPGA",
booktitle = "Proc. 12th Iberchip Workshop (IWS)",
address = "San Jose (Costa Rica)",
month = "March",
year = "2006",
pages = "242--245"
};
@inproceedings{viejo06-1,
author = "J. Viejo and E. Ostua and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and D. Guerrero",
title = "Diseño e implementación óptima de periféricos de DSP con System Generator para MicroBlaze",
booktitle = "Proc. 12th Iberchip Workshop (IWS)",
address = "San Jose (Costa Rica)",
month = "March",
year = "2006",
pages = "49--52"
};
@inproceedings{viejo06-2,
author = "J. Viejo and M.~J. Bellido and A. Millan and E. Ostua and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero",
title = "Efficient design and implementation on FPGA of a MicroBlaze peripheral for processing direct electrical networks measurements",
booktitle = "Proc. 1st IEEE International Symposium on Industrial Embedded Systems (IES)",
address = "Antibes Juan-Les-Pins (France)",
month = "October",
year = "2006",
pages = "--",
isbn = "1-4244-0777-X"
};
@inproceedings{viejo06-3,
author = "J. Viejo and M.~J. Bellido and A. Millan and E. Ostua and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero",
title = "DSP peripheral on FPGA for electrical networks measurements",
booktitle = "Proc. 21th Conference on Design of Circuits and Integrated Systems (DCIS)",
address = "Barcelona (Spain)",
month = "November",
year = "2006",
pages = "--",
isbn = "978-84-690-4144-4"
};
%%%% 2005 %%%%
@inproceedings{guerrero05-1,
author = "D. Guerrero and M.~J. Bellido and J. Juan",
title = "CMOS digital design techniques for low power and high speed",
booktitle = "Proc. Conference on Design, Automation and Test in Europe (DATE)",
address = "Munich (Germany)",
month = "March",
year = "2005",
pages = "--",
isbn = "0-7695-2288-2"
};
@inproceedings{guerrero05-2,
author = "D. Guerrero and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and E. Ostua and J. Viejo",
title = "Algorithms to get the maximum operation frequency for skew-tolerant clocking schemes",
booktitle = "Proc. Microtechnologies for the New Millennium 2005, SPIE",
address = "Sevilla (Spain)",
month = "May",
year = "2005",
pages = "467--478",
isbn = "9780819458322"
}
@inproceedings{millan05-1,
author = "A. Millan and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua and J. Viejo",
title = "Efficient design of a FFT/IFFT-64 module on ASIC",
booktitle = "Proc. 11th Iberchip Workshop (IWS)",
address = "Salvador de Bahia (Brazil)",
month = "March",
year = "2005",
pages = "305--306",
isbn = "959-261-105-X"
}
@inproceedings{millan05-2,
author = "A. Millan and M.~J. Bellido and J. Juan",
title = "Optimization techniques for dynamic behavior modeling of digital CMOS VLSI circuits in nanometric technologies",
booktitle = "Proc. PhD Research In Micro-Electronics and Electronics (PRIME)",
address = "Lausanne (Switzerland)",
month = "July",
year = "2005",
pages = "374--377",
isbn = "0-78039345-7"
}
@inproceedings{millan05-3,
author = "A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua and J. Viejo",
title = "Application of Internode model to global power consumption estimation in SCMOS gates",
booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
series = "Lecture Notes in Computer Science",
volume = "3728",
month = "September",
year = "2005",
pages = "337--347",
publisher = "Springer Berlin Heidelberg",
isbn = "978-3-540-29013-1",
doi = "10.1007/11556930_35"
}
@inproceedings{millan05-4,
author = "A. Millan and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua and J. Viejo",
title = "Analysis of internal power consumption in SCMOS gates in submicronic/nanometric technologies",
booktitle = "Proc. 20th Conference on Design of Circuits and Integrated Systems (DCIS)",
address = "Lisboa (Portugal)",
month = "November",
year = "2005",
pages = "--",
isbn = "972-99387-2-5"
}
@inproceedings{ostua05,
author = "E. Ostua and J. Viejo and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and D. Guerrero",
title = "Entorno de desarrollo para SOC basado en el microprocesador LEON2",
booktitle = "Proc. 11th Iberchip Workshop (IWS)",
address = "Salvador de Bahia (Brazil)",
month = "March",
year = "2005",
pages = "429--430",
isbn = "959-261-105-X"
}
@inproceedings{clavijo05-1,
author = "P. Ruiz-de-Clavijo and M.~J. Bellido and J. Juan",
title = "HALOTIS - High accurate logic timing simulator",
booktitle = "Proc. PhD Research In Micro-Electronics and Electronics (PRIME)",
address = "Lausanne (Switzerland)",
month = "July",
year = "2005",
pages = "191--194",
isbn = "0-78039345-7"
}
@inproceedings{clavijo05-2,
author = "P. Ruiz-de-Clavijo and J. Juan and M.~J. Bellido and A. Millan and D. Guerrero and E. Ostua and J. Viejo",
title = "Logic-Level Fast Current Simulation for Digital CMOS Circuits",
booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
series = "Lecture Notes in Computer Science",
volume = "3728",
month = "September",
year = "2005",
pages = "425--435",
publisher = "Springer Berlin Heidelberg",
isbn = "978-3-540-29013-1",
doi = "10.1007/11556930_44"
}
@inproceedings{viejo05-1,
author = "J. Viejo and E. Ostua and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and D. Guerrero",
title = "Diseño, implementacion y aplicacion a SOC del microprocesador Picoblaze",
booktitle = "Proc. 11th Iberchip Workshop (IWS)",
address = "Salvador de Bahia (Brazil)",
month = "March",
year = "2005",
pages = "431--432",
isbn = "959-261-105-X"
};
%%%% 2004 %%%%
@inproceedings{guerrero04,
author = "D. Guerrero and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and E. Ostua",
title = "Four phase alternating latches clocking scheme for CMOS sequential circuits",
booktitle = "Proc. 19th Conference on Design of Circuits and Integrated Systems (DCIS)",
address = "Bordeaux (France)",
month = "November",
year = "2004",
pages = "780--783",
isbn = "2-9522971-0-X"
};
@inproceedings{millan04,
author = "A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua",
title = "Signal sampling based transition modeling for digital gates characterization",
booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
series = "Lecture Notes in Computer Science",
volume = "3254",
month = "September",
year = "2004",
pages = "829--837",
publisher = "Springer Berlin Heidelberg",
isbn = "978-3-540-23095-3",
doi = "10.1007/978-3-540-30205-6_85"
}
%%%% 2003 %%%%
@inproceedings{guerrero03-1,
author = "D. Guerrero and G. Wilke and J.~L. Guntzel and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and A. Millan",
title = "Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits",
booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
series = "Lecture Notes in Computer Science",
volume = "2799",
month = "September",
year = "2003",
pages = "501--510",
publisher = "Springer Berlin Heidelberg",
isbn = "978-3-540-20074-1",
doi = "10.1007/978-3-540-39762-5_56"
}
@inproceedings{guerrero03-2,
author = "D. Guerrero and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and G. Wilke and J.~L. Güntzel",
title = "Estimation of floating cube delay using transistor path computational delay models for CMOS circuits",
booktitle = "Proc. 18th Conference on Design of Circuits and Integrated Systems (DCIS)",
address = "Ciudad Real (Spain)",
month = "November",
year = "2003",
pages = "95--99",
isbn = "84-87087-40-X"
};
@inproceedings{millan03-1,
author = "A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua",
title = "Using sampled input signals for SCMOS gates characterization",
booktitle = "Proc. 18th Conference on Design of Circuits and Integrated Systems (DCIS)",
address = "Ciudad Real (Spain)",
month = "November",
year = "2003",
pages = "275--280",
isbn = "84-87087-40-X"
};
@inproceedings{millan03-2,
author = "A. Millan and M.~J. Bellido and J. Juan and D. Guerrero and P. Ruiz-de-Clavijo and E. Ostua",
title = "Internode: Internal node logic computational model",
booktitle = "Proc. 36th Annual Simulation Symposium (Advanced Simulation Technologies Conference, ASTC)",
address = "Orlando, FL (United States of America)",
month = "March",
year = "2003",
pages = "241--248",
isbn = "0-7695-1911-3"
};
@inproceedings{millan03-3,
author = "A. Millan and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua",
title = "Diseño eficiente de un módulo FFT/IFFT-64 sobre FPGA",
booktitle = "Proc. 3rd Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
address = "Madrid (Spain)",
month = "September",
year = "2003",
pages = "107--114",
isbn = "84-600-9928-8"
};
@inproceedings{ostua03-1,
author = "E. Ostua and M.~J. Bellido and P. Ruiz-de-Clavijo and A. Barriga and A. Millan and D. Guerrero and J. Juan",
title = "Diseño e implementación sobre FPGA de un microprocesador empotrable en SOC de control",
booktitle = "Proc. 3rd Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
address = "Madrid (Spain)",
month = "September",
year = "2003",
pages = "385--392",
isbn = "84-600-9928-8"
};
@inproceedings{ostua03-2,
author = "E. Ostua and M.~J. Bellido and A. Barriga and P. Ruiz-de-Clavijo and J. Juan and A. Millan and D. Guerrero",
title = "Diseño e implementación sobre FPGA de un microprocesador empotrable en SOC de Control",
booktitle = "Proc. Seminario Anual de Automática, Electrónica Industrial e Instrumentación (SAAEI, Annual Seminar on Automatic Control, Industrial Electronics and Instrumentation)",
address = "Vigo (Spain)",
month = "September",
year = "2003",
pages = "--",
isbn = "84-688-3055-6"
};
@inproceedings{clavijo03,
author = "P. Ruiz-de-Clavijo and J. Juan and J.~R. Fernandes and M.~J. Bellido and A. Millan and D. Guerrero",
title = "Delay degradation effect in current balanced logic cells",
booktitle = "Proc. 18th Conference on Design of Circuits and Integrated Systems (DCIS)",
address = "Ciudad Real (Spain)",
month = "November",
year = "2003",
pages = "163--165",
isbn = "84-87087-40-X"
};
%%%% 2002 %%%%
@inproceedings{baena02,
author = "C. Baena and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and C.~J. Jimenez and M. Valencia",
title = "Measurement of the switching activity of CMOS digital circuits at the gate level",
booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
series = "Lecture Notes in Computer Science",
volume = "2451",
month = "September",
year = "2002",
pages = "353--362",
publisher = "Springer Berlin Heidelberg",
isbn = "978-3-540-44143-4",
doi = "10.1007/3-540-45716-X_35"
}
@inproceedings{estevez02,
author = "M. Estevez and M.~J. Bellido and C.~J. Jimenez and J. Juan",
title = "Design of a Microprocessor for SOC applications",
booktitle = "Proc. 4th European Workshop on Microelectronics Education (EWME)",
address = "Vigo (Spain)",
month = "May",
year = "2002",
pages = "149--152",
isbn = "84-267-1325-4"
};
@inproceedings{guerrero02,
author = "D. Guerrero and M.~J. Bellido and J. Juan and P. Paulino and A. Millan",
title = "Two phase alternating latches clocking scheme for CMOS sequential circuits",
booktitle = "Proc. 17th Conference on Design of Circuits and Integrated Systems (DCIS)",
address = "Santander (Spain)",
month = "November",
year = "2002",
pages = "159--162"
};
@inproceedings{millan02-1,
author = "A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and D. Guerrero",
title = "Characterization of normal propagation delay for Delay Degradation Model (DDM)",
booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
series = "Lecture Notes in Computer Science",
volume = "2451",
month = "September",
year = "2002",
pages = "477--486",
publisher = "Springer Berlin Heidelberg",
isbn = "978-3-540-44143-4",
doi = "10.1007/3-540-45716-X_48"
}
@inproceedings{millan02-2,
author = "A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and D. Guerrero",
title = "Integration of a characterization method for normal propagation delay into AUTODDM",
booktitle = "Proc. 17th Conference on Design of Circuits and Integrated Systems (DCIS)",
address = "Santander (Spain)",
month = "November",
year = "2002",
pages = "93--97"
};
@inproceedings{clavijo02,
author = "P. Ruiz-de-Clavijo and J. Juan and M.~J. Bellido and A. Millan and D. Guerrero",
title = "Efficient and fast current curve estimation of CMOS digital circuits at the logic level",
booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
series = "Lecture Notes in Computer Science",
volume = "2451",
month = "September",
year = "2002",
pages = "400--408",
publisher = "Springer Berlin Heidelberg",
isbn = "978-3-540-44143-4",
doi = "10.1007/3-540-45716-X_40"
}
%%%% 2001 %%%%
@inproceedings{baena01,
author = "C. Baena and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and C.~J. Jimenez and M. Valencia",
title = "Simulation-driven switching activity evaluation of CMOS digital circuits",
booktitle = "Proc. 16th Conference on Design of Circuits and Integrated Systems (DCIS)",
address = "Porto (Portugal)",
month = "November",
year = "2001",
pages = "608--612"
};
@inproceedings{bellido01,
author = "M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and A.~J. Acosta and M. Valencia",
title = "Gate-level simulation of CMOS circuits using the IDDM model",
booktitle = "Proc. IEEE International Symposium on Circuits and Systems (ISCAS)",
address = "Darling Harbour, Sydney (Australia)",
month = "May",
year = "2001",
pages = "483--486",
isbn = "0-7803-6687-5"
};
@inproceedings{juan01-1,
author = "J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and C.~J. Jimenez and C. Baena and M. Valencia",
title = "Logic-timing simulation using the Degradation Delay Model",
booktitle = "Proc. International Workshop on Logic and Synthesis (IWLS)",
address = "Granlibakken, CA (United States of America)",
month = "June",
year = "2001",
pages = "237--242"
};
@inproceedings{juan01-2,
author = "J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and C. Baena and M. Valencia",
title = "AUTODDM: AUTOmatic characterization tool for the Delay Degradation Model",
booktitle = "Proc. International Conference on Electronics, Circuits and Systems (ICECS)",
address = "Malta",
month = "September",
year = "2001",
pages = "1631--1634",
isbn = "0-7803-7057-0"
};
@inproceedings{juan01-3,
author = "J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and C. Baena and M. Valencia",
title = "DDM characterization methodology and automation",
booktitle = "Proc. 11th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)",
address = "Yverdon-Les-Bains (Switzerland)",
month = "September",
year = "2001",
pages = "5.2.1--5.2.10"
};
@inproceedings{clavijo01-1,
author = "P. Ruiz-de-Clavijo and M.~J. Bellido and J. Juan and C. Baena",
title = "ISS: Interactive Simulation System",
booktitle = "Proc. 16th Conference on Design of Circuits and Integrated Systems (DCIS)",
address = "Porto (Portugal)",
month = "November",
year = "2001",
pages = "410--413"
};
@inproceedings{clavijo01-2,
author = "P. Ruiz-de-Clavijo and J. Juan and M.~J. Bellido and A.~J. Acosta and M. Valencia",
title = "HALOTIS: High Accuracy LOgic TIming Simulator with inertial and degradation delay model",
booktitle = "Proc. Conference on Design, Automation and Test in Europe (DATE)",
address = "Munich (Germany)",
month = "March",
year = "2001",
pages = "467--471",
isbn = "0-7695-0993-2"
};
%%%% 2000 %%%%
@inproceedings{acosta00,
author = "A.~J. Acosta and R. Jimenez and J. Juan and M.~J. Bellido and M. Valencia",
title = "Influence of clocking strategies on the design of low switching-noise digital and mixed-signal VLSI circuits",
booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
series = "Lecture Notes in Computer Science",
volume = "1918",
month = "September",
year = "2000",
pages = "316--326",
publisher = "Springer Berlin Heidelberg",
isbn = "978-3-540-41068-3",
doi = "10.1007/3-540-45373-3_33"
}
@inproceedings{juan00-1,
author = "J. Juan and P. Ruiz-de-Clavijo and M.~J. Bellido and A.~J. Acosta and M. Valencia",
title = "Inertial and Degradation Delay Model for CMOS Logic Gates",
booktitle = "Proc. IEEE International Symposium on Circuits and Systems (ISCAS)",
address = "Geneva (Switzerland)",
month = "May",
year = "2000",
pages = "459--462",
isbn = "0-7803-5485-0"
}
@inproceedings{juan00-2,
author = "J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and A.~J. Acosta and M. Valencia",
title = "Degradation delay model extension to CMOS gates",
booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
series = "Lecture Notes in Computer Science",
volume = "1918",
month = "September",
year = "2000",
pages = "149--158",
publisher = "Springer Berlin Heidelberg",
isbn = "978-3-540-41068-3",
doi = "10.1007/3-540-45373-3_15"
}
@inproceedings{juan00-3,
author = "J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and A.~J. Acosta and M. Valencia",
title = "Gate-Level Modeling of the Delay Degradation Effect",
booktitle = "Proc. 15th Conference on Design of Circuits and Integrated Systems (DCIS)",
address = "Montpellier - Le Corum (France)",
month = "November",
year = "2000",
pages = "537--542"
}