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Publicaciones

Libros y capítulos de libros

"2012" (1)

  • (“2012”) “Open Development Platform for Embedded Systems”. In “Grid Computing – Technology and Applications, Widespread Coverage and New Horizons”. pp. “311–324”. “InTech, Croatia”. ISBN: “978-953-51-0604-3”. doi bibtex

"2006" (1)

  • (“2006”) “Logic-timing Simulation and the Degradation Delay Model”. “Imperial College Press, United Kingdom”. ISBN: “1-86094-589-9”. bibtex

"2000" (1)

  • (“2000”) “Temporización en Circuitos Integrados Digitales CMOS”. “Marcombo, Barcelona (Spain)”. ISBN: “84-267-1246-0”. bibtex

Patentes

2018 (1)

  • (“November” 2018) Dispositivo Electrónico Calculador de Funciones Trigonométricas y Usos del Mismo. P201831133. web bibtex

2016 (1)

  • (“October” 2016) Circuito Electrónico Digital para el Cálculo de Senos y Cosenos de Múltiplos de un Ángulo. P201600865. web bibtex

Artículos en revistas

2023 (1)

  • (2023) IRIS: An embedded secure boot for IoT devices. Internet of Things (Netherlands) 23 ISSN: 2542-6605. doi web bibtex

2021 (2)

  • (2021) “Embedded LUKS (E-LUKS): a hardware solution to IoT security”. “Electronics” 10 (23) pp. 1–22. ISSN: “2079-9292”. doi bibtex
  • (2021) “An Integrated Digital System Design Framework with On-Chip Functional Verification and Performance Evaluation”. “IEEE Access” “9” (“”) pp. “161383–161394”. ISSN: 2169-3536. doi bibtex

2020 (2)

  • (2020) “Using the complement of the cosine to compute trigonometric functions”. “EURASIP Journal on Advances in Signal Processing” “2020” (“35”) pp. “1–21”. ISSN: 1687-6172. doi bibtex
  • (2020) “Address-encoded byte order”. “Microprocessors and Microsystems (MicPro)” “78” pp. “1–9”. ISSN: “0141-9331”. doi bibtex

2019 (1)

  • (2019) “High-Performance Time Server Core for FPGA System-on-Chip”. “Electronics” “8” (“5”) pp. “1–28”. ISSN: “2079-9292”. doi bibtex

2017 (1)

  • (2017) “Minimalistic SDHC-SPI hardware reader module for boot loader applications”. “Microelectronics Journal” “67” (“”) pp. “32–37”. ISSN: “0026-2692”. doi bibtex

2016 (1)

  • (2016) “Fast Hardware Implementations of Static P Systems”. “Computing and Informatics” “35” (“3”) pp. “687–718”. ISSN: “1335-9150 ”. bibtex

"2013" (1)

  • (“2013”) “NanoFS: a hardware-oriented file system”. “Electronics Letters” “49” (“19”) pp. “1216–1218”. “The Institution of Engineering and Technology”. “England”. ISSN: “0013-5194”. doi bibtex

"2012" (1)

  • (“2012”) “Long-term on-chip verification of systems with logical events scattered in time”. “Microprocessors and Microsystems” “36” (“5”) pp. “402–408”. “Elsevier”. “United Kingdom”. ISSN: “0141-9331”. doi bibtex

"2011" (2)

  • (“2011”) “Fast-convergence microsecond-accurate clock discipline algorithm for hardware implementation”. “IEEE Transactions on Instrumentation and Measurement” “60” (“12”) pp. “3961–3963”. “IEEE Press”. “United States of America”. ISSN: “0018-9456”. doi bibtex
  • (“2011”) “Studying the viability of static CMOS gates with a large number of inputs when using separate transistor wells”. “Journal of Low Power Electronics” “7” (“3”) pp. “444–452”. “American Scientific Publishers”. “United States of America”. ISSN: “1546-1998”. doi bibtex

"2010" (1)

  • (“2010”) “Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies”. “Journal of Low Power Electronics” “6” (“1”) pp. “93–102”. “American Scientific Publishers”. “United States of America”. ISSN: “1546-1998”. doi bibtex

"2007" (1)

  • (“2007”) “Improving the performance of static CMOS gates by using independent bodies”. “Journal of Low Power Electronics” “3” (“1”) pp. “70–77”. “American Scientific Publishers”. “United States of America”. ISSN: “1546-1998”. doi bibtex

"2006" (2)

  • (“2006”) “Automated performance evaluation of skew-tolerant clocking schemes”. “International Journal of Electronics” “93” (“12”) pp. “819–842”. “Taylor & Francis”. “United Kingdom”. ISSN: “0020-7217”. doi bibtex
  • (“2006”) “Accurate logic-level current estimation for digital CMOS circuits”. “Journal of Low Power Electronics” “2” (“”) pp. “87–94”. “American Scientific Publishers”. “United States of America”. ISSN: “1546-1998”. doi bibtex

"2001" (1)

  • (“2001”) “Switching activity evaluation of CMOS digital circuits using logic timing simulation”. “IEE Electronics Letters” “37” (“9”) pp. “555–557”. “IEE”. “United Kingdom of Great Britain and Northern Ireland”. ISSN: “0013-5194”. doi bibtex

"2000" (1)

  • (“2000”) “Logical modelling of delay degradation effect in static CMOS gates”. “IEE Proceedings on Circuits Devices Systems Engineering” “147” (“2”) pp. “107–117”. “IEE”. “United Kingdom of Great Britain and Northern Ireland”. ISSN: “1350-2409”. doi bibtex

Contribuciones a congresos

2015 (1)

  • (June 2015) evercodeML: A formal language for SoC integration. In Electronic System Level Synthesis Conference (ESLsyn), 2015. pp. 23-26. ISBN: 979-10-92279-13-9. ISSN: 2117-4628. web
    • Abstract bibtex

2013 (2)

  • (“February” 2013) “XML-based Description Language for Heterogeneous and Highly-configurable IP-core Integration”. In “Proc. 19th Iberchip Workshop (IWS)”. pp. “–”. “Cusco (Peru)”. ISBN: “978-1-4673-4899-7”. bibtex
  • (2013) Network Time Synchronization: A Full Hardware Approach. In Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Lecture Notes in Computer Science 7606 pp. 225-234. Springer Berlin Heidelberg. ISBN: 978-3-642-36156-2. doi web bibtex

"2018" (1)

  • (“September” “2018”) “OpenRISC hardware bootloader over WiFi”. In “The open source digital design conference (ORConf)”. pp. “”. “Gdansk (Poland)”. bibtex

"2016" (2)

  • (“February” “2016”) “Case study: performance and power analysis of a dynamically reconfigurable hardware/software cryptosystem”. In “Proc. 22th Iberchip Workshop (IWS)”. pp. “112–115”. “Florianopolis (Brazil)”. bibtex
  • (“February” “2016”) “Building a basic membrane computer”. In “Proc. 14th Brainstorming Week on Membrane Computing (BWMC)”. pp. “269–280”. “Universidad de Sevilla, Sevilla (Spain)”. bibtex

"2013" (1)

  • (“2013”) “Fast Hardware Implementations of P Systems”. In “Membrane Computing”. Lecture Notes in Computer Science 7762 pp. 404-423. Springer Berlin Heidelberg. ISBN: 978-3-642-36750-2. doi web bibtex

"2012" (1)

  • (“September” “2012”) “Diseño e implementación de un controlador domótico reconfigurable basado en hardware y software libre”. In “Proc. 12th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)”. pp. “161–166”. “Elche (Spain)”. ISBN: “978-84-695-4470-9”. bibtex

"2011" (2)

  • (“April” “2011”) “Implementation of a configuration server for a hardware SNTP synchronization platform based on FPGA”. In “Proc. 7th Southern Conference on Programmable Logic (SPL)”. pp. “239–244”. “Cordoba (Argentina)”. ISBN: “978-1-4244-8846-9”. bibtex
  • (“April” “2011”) “Python as a Hardware Description Language: A Case Study”. In “Proc. 7th Southern Conference on Programmable Logic (SPL)”. pp. “117–122”. “Cordoba (Argentina)”. ISBN: “978-1-4244-8846-9”. bibtex

"2010" (4)

  • (“November” “2010”) “Long-term on-chip verification of systems with logical events scattered in time”. In “Proc. 25th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “323–326”. “Lanzarote (Spain)”. ISBN: “978-84-693-7393-4”. bibtex
  • (“September” “2010”) “Verificación on-chip de larga duración de sistemas con eventos lógicos dispersos en el tiempo”. In “Proc. 10th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)”. pp. “269–276”. “Valencia (Spain)”. ISBN: “978-84-92812-56-1”. bibtex
  • (“July” “2010”) “Design and implementation of a suitable core for on-chip long-term verification”. In “Proc. 5th IEEE International Symposium on Industrial Embedded Systems (SIES)”. pp. “234–237”. “Trento (Italy)”. ISBN: “978-1-4244-5840-0”. bibtex
  • (“February” “2010”) “Implementación sobre FPGA de un cliente SNTP usando MicroBlaze”. In “Proc. 16th Iberchip Workshop (IWS)”. pp. “–”. “Iguazu Falls (Brazil)”. bibtex

"2009" (8)

  • (“September” “2009”) “Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates”. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “5349” pp. “389–398”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-95947-2”. doi bibtex
  • (“September” “2009”) “Aplicación de Picoblaze como Emulador/Receptor de un GPS en el diseño hardware de un cliente/servidor SNTP”. In “Proc. 9th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)”. pp. “193–202”. “Madrid (Spain)”. ISBN: “978-84-8138-832-9”. bibtex
  • (“September” “2009”) “Implementación sobre FPGA de un cliente SNTP de bajo coste y alta precisión”. In “Proc. 9th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)”. pp. “359–366”. “Madrid (Spain)”. ISBN: “978-84-8138-832-9”. bibtex
  • (“September” “2009”) “Usando Python como HDL: Estudio comparativo de resultados basado en el desarrollo de un periférico real”. In “Proc. 9th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)”. pp. “33–42”. “Madrid (Spain)”. ISBN: “978-84-8138-832-9”. bibtex
  • (“August” “2009”) “Efficient techniques and methodologies for embedded system design using free hardware and open standards”. In “Proc. 19th International Conference on Field Programmable Logic and Applications (FPL)”. pp. “719–720”. “Prague (Czech Republic)”. ISBN: “978-1-4244-3892-1”. bibtex
  • (“April” “2009”) “Delay and Power Consumption of Static Bulk-CMOS Gates Using Independent Bodies”. In “Proc. 4th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)”. pp. “191–196”. “Cairo (Egypt)”. ISBN: “978-1-4244-4321-5”. bibtex
  • (“March” “2009”) “Performance Analysis of Bulk-CMOS Gates Using Separated Wells”. In “Proc. 15th Iberchip Workshop (IWS)”. pp. “54–59”. “Buenos Aires (Argentina)”. bibtex
  • (“March” “2009”) “Accurate and compact implementation of a hardware SNTP Client”. In “Proc. 15th Iberchip Workshop (IWS)”. pp. “504–509”. “Buenos Aires (Argentina)”. bibtex

"2008" (8)

  • (“September” “2008”) “Metodología de Diseño de SoC basada en OpenRisc sobre FPGA con Cores y Herramientas Libres”. In “Proc. 8th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)”. pp. “247–256”. “Madrid (Spain)”. ISBN: “978-84-612-5635-8”. bibtex
  • (“June” “2008”) “Building a SoC for industrial applications based on LEON microprocessor and a GNU/Linux distribution”. In “Proc. 2008 IEEE International Symposium on Industrial Electronics (ISIE)”. pp. “1727–1732”. “Cambridge (United Kingdom)”. ISBN: “978­-1­-4244­-1666-­0”. bibtex
  • (“June” “2008”) “Design and implementation of a SNTP client on FPGA”. In “Proc. 2008 IEEE International Symposium on Industrial Electronics (ISIE)”. pp. “1971–1975”. “Cambridge (United Kingdom)”. ISBN: “978­-1­-4244­-1666-­0”. bibtex
  • (“May” “2008”) “Delay and Power Consumption of Static Bulk-CMOS Gates Using Independent Bodies”. In “Proc. 7th Journées d'études Faible Tension Faible Consommation (FTFC)”. pp. “105–110”. “Louvain-la-Neuve (Belgium)”. bibtex
  • (“April” “2008”) “Using Independent Bodies in Bulk-CMOS Gates”. In “Proc. 11th IEEE Symposium on Low-Power and High-Speed Chips (COOLChips)”. pp. “221”. “Yokohama (Japan)”. bibtex
  • (“April” “2008”) “Internal Power Dissipation of Static CMOS Gates in UDSM Technologies”. In “Proc. 11th IEEE Symposium on Low-Power and High-Speed Chips (COOLChips)”. pp. “127”. “Yokohama (Japan)”. bibtex
  • (“March” “2008”) “Digital Data Processing Peripheral Design for an Embedded Application Based on the Microblaze Soft Core”. In “Proc. 4th Southern Conference on Programmable Logic (SPL)”. pp. “197–200”. “San Carlos de Bariloche (Argentina)”. ISBN: “978-1-4244-1992-0”. bibtex
  • (“March” “2008”) “Implementation of a FFT/IFFT module on FPGA: Comparison of methodologies”. In “Proc. 4th Southern Conference on Programmable Logic (SPL)”. pp. “7–11”. “San Carlos de Bariloche (Argentina)”. ISBN: “978-1-4244-1992-0”. bibtex

"2007" (7)

  • (“November” “2007”) “The effect of using separated bodies over static power consumption in Static Bulk-CMOS gates”. In “Proc. 22th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “181–185”. “Seville (Spain)”. ISBN: “978-84690-8629-2”. bibtex
  • (“September” “2007”) “Static power consumption in CMOS gates using independent bodies”. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “4644” pp. “404–412”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-74441-2”. doi bibtex
  • (“September” “2007”) “Un ejemplo de implantación de una distribución Linux en un SoC basado en hardware libre”. In “Proc. 7th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)”. pp. “85–92”. “Zaragoza (Spain)”. ISBN: “978-84-9732-600-1”. bibtex
  • (“September” “2007”) “Evaluación de metodologías para la implementación de un módulo FFT/IFFT sobre FPGA mediante herramientas a nivel de sistema”. In “Proc. 7th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)”. pp. “205–211”. “Zaragoza (Spain)”. ISBN: “978-84-9732-600-1”. bibtex
  • (“July” “2007”) “Design of a FFT/IFFT module as an IP core suitable for embedded systems”. In “Proc. 2nd IEEE International Symposium on Industrial Embedded Systems (SIES)”. pp. “337–340”. “Lisbon (Portugal)”. ISBN: “1-4244-0840-7”. bibtex
  • (“May” “2007”) “Automatic logic synthesis for parallel alternating latches clocking schemes”. In “Proc. Microtechnologies for the New Millennium 2007, SPIE”. pp. “61–69”. “Maspalomas (Spain)”. ISBN: “9780819467188”. bibtex
  • (“March” “2007”) “Síntesis lógica automatizada para esquemas de temporización de latches alternantes”. In “Proc. 13th Iberchip Workshop (IWS)”. pp. “349–350”. “Lima (Peru)”. ISBN: “978-9972-242-09-0”. bibtex

"2006" (4)

  • (“November” “2006”) “DSP peripheral on FPGA for electrical networks measurements”. In “Proc. 21th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “–”. “Barcelona (Spain)”. ISBN: “978-84-690-4144-4”. bibtex
  • (“October” “2006”) “Efficient design and implementation on FPGA of a MicroBlaze peripheral for processing direct electrical networks measurements”. In “Proc. 1st IEEE International Symposium on Industrial Embedded Systems (IES)”. pp. “–”. “Antibes Juan-Les-Pins (France)”. ISBN: “1-4244-0777-X”. bibtex
  • (“March” “2006”) “A SOC design methodology for LEON2 on FPGA”. In “Proc. 12th Iberchip Workshop (IWS)”. pp. “242–245”. “San Jose (Costa Rica)”. bibtex
  • (“March” “2006”) “Diseño e implementación óptima de periféricos de DSP con System Generator para MicroBlaze”. In “Proc. 12th Iberchip Workshop (IWS)”. pp. “49–52”. “San Jose (Costa Rica)”. bibtex

"2005" (10)

  • (“November” “2005”) “Analysis of internal power consumption in SCMOS gates in submicronic/nanometric technologies”. In “Proc. 20th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “–”. “Lisboa (Portugal)”. ISBN: “972-99387-2-5”. bibtex
  • (“September” “2005”) “Application of Internode model to global power consumption estimation in SCMOS gates”. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “3728” pp. “337–347”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-29013-1”. doi bibtex
  • (“September” “2005”) “Logic-Level Fast Current Simulation for Digital CMOS Circuits”. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “3728” pp. “425–435”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-29013-1”. doi bibtex
  • (“July” “2005”) “Optimization techniques for dynamic behavior modeling of digital CMOS VLSI circuits in nanometric technologies”. In “Proc. PhD Research In Micro-Electronics and Electronics (PRIME)”. pp. “374–377”. “Lausanne (Switzerland)”. ISBN: “0-78039345-7”. bibtex
  • (“July” “2005”) “HALOTIS - High accurate logic timing simulator”. In “Proc. PhD Research In Micro-Electronics and Electronics (PRIME)”. pp. “191–194”. “Lausanne (Switzerland)”. ISBN: “0-78039345-7”. bibtex
  • (“May” “2005”) “Algorithms to get the maximum operation frequency for skew-tolerant clocking schemes”. In “Proc. Microtechnologies for the New Millennium 2005, SPIE”. pp. “467–478”. “Sevilla (Spain)”. ISBN: “9780819458322”. bibtex
  • (“March” “2005”) “CMOS digital design techniques for low power and high speed”. In “Proc. Conference on Design, Automation and Test in Europe (DATE)”. pp. “–”. “Munich (Germany)”. ISBN: “0-7695-2288-2”. bibtex
  • (“March” “2005”) “Efficient design of a FFT/IFFT-64 module on ASIC”. In “Proc. 11th Iberchip Workshop (IWS)”. pp. “305–306”. “Salvador de Bahia (Brazil)”. ISBN: “959-261-105-X”. bibtex
  • (“March” “2005”) “Entorno de desarrollo para SOC basado en el microprocesador LEON2”. In “Proc. 11th Iberchip Workshop (IWS)”. pp. “429–430”. “Salvador de Bahia (Brazil)”. ISBN: “959-261-105-X”. bibtex
  • (“March” “2005”) “Diseño, implementacion y aplicacion a SOC del microprocesador Picoblaze”. In “Proc. 11th Iberchip Workshop (IWS)”. pp. “431–432”. “Salvador de Bahia (Brazil)”. ISBN: “959-261-105-X”. bibtex

"2004" (2)

  • (“November” “2004”) “Four phase alternating latches clocking scheme for CMOS sequential circuits”. In “Proc. 19th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “780–783”. “Bordeaux (France)”. ISBN: “2-9522971-0-X”. bibtex
  • (“September” “2004”) “Signal sampling based transition modeling for digital gates characterization”. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “3254” pp. “829–837”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-23095-3”. doi bibtex

"2003" (8)

  • (“November” “2003”) “Estimation of floating cube delay using transistor path computational delay models for CMOS circuits”. In “Proc. 18th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “95–99”. “Ciudad Real (Spain)”. ISBN: “84-87087-40-X”. bibtex
  • (“November” “2003”) “Using sampled input signals for SCMOS gates characterization”. In “Proc. 18th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “275–280”. “Ciudad Real (Spain)”. ISBN: “84-87087-40-X”. bibtex
  • (“November” “2003”) “Delay degradation effect in current balanced logic cells”. In “Proc. 18th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “163–165”. “Ciudad Real (Spain)”. ISBN: “84-87087-40-X”. bibtex
  • (“September” “2003”) “Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits”. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “2799” pp. “501–510”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-20074-1”. doi bibtex
  • (“September” “2003”) “Diseño eficiente de un módulo FFT/IFFT-64 sobre FPGA”. In “Proc. 3rd Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)”. pp. “107–114”. “Madrid (Spain)”. ISBN: “84-600-9928-8”. bibtex
  • (“September” “2003”) “Diseño e implementación sobre FPGA de un microprocesador empotrable en SOC de control”. In “Proc. 3rd Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)”. pp. “385–392”. “Madrid (Spain)”. ISBN: “84-600-9928-8”. bibtex
  • (“September” “2003”) “Diseño e implementación sobre FPGA de un microprocesador empotrable en SOC de Control”. In “Proc. Seminario Anual de Automática, Electrónica Industrial e Instrumentación (SAAEI, Annual Seminar on Automatic Control, Industrial Electronics and Instrumentation)”. pp. “–”. “Vigo (Spain)”. ISBN: “84-688-3055-6”. bibtex
  • (“March” “2003”) “Internode: Internal node logic computational model”. In “Proc. 36th Annual Simulation Symposium (Advanced Simulation Technologies Conference, ASTC)”. pp. “241–248”. “Orlando, FL (United States of America)”. ISBN: “0-7695-1911-3”. bibtex

"2002" (6)

  • (“November” “2002”) “Two phase alternating latches clocking scheme for CMOS sequential circuits”. In “Proc. 17th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “159–162”. “Santander (Spain)”. bibtex
  • (“November” “2002”) “Integration of a characterization method for normal propagation delay into AUTODDM”. In “Proc. 17th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “93–97”. “Santander (Spain)”. bibtex
  • (“September” “2002”) “Measurement of the switching activity of CMOS digital circuits at the gate level”. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “2451” pp. “353–362”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-44143-4”. doi bibtex
  • (“September” “2002”) “Characterization of normal propagation delay for Delay Degradation Model (DDM)“. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “2451” pp. “477–486”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-44143-4”. doi bibtex
  • (“September” “2002”) “Efficient and fast current curve estimation of CMOS digital circuits at the logic level”. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “2451” pp. “400–408”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-44143-4”. doi bibtex
  • (“May” “2002”) “Design of a Microprocessor for SOC applications”. In “Proc. 4th European Workshop on Microelectronics Education (EWME)”. pp. “149–152”. “Vigo (Spain)”. ISBN: “84-267-1325-4”. bibtex

"2001" (7)

  • (“November” “2001”) “Simulation-driven switching activity evaluation of CMOS digital circuits”. In “Proc. 16th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “608–612”. “Porto (Portugal)”. bibtex
  • (“November” “2001”) “ISS: Interactive Simulation System”. In “Proc. 16th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “410–413”. “Porto (Portugal)”. bibtex
  • (“September” “2001”) “AUTODDM: AUTOmatic characterization tool for the Delay Degradation Model”. In “Proc. International Conference on Electronics, Circuits and Systems (ICECS)”. pp. “1631–1634”. “Malta”. ISBN: “0-7803-7057-0”. bibtex
  • (“September” “2001”) “DDM characterization methodology and automation”. In “Proc. 11th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)”. pp. “5.2.1–5.2.10”. “Yverdon-Les-Bains (Switzerland)”. bibtex
  • (“June” “2001”) “Logic-timing simulation using the Degradation Delay Model”. In “Proc. International Workshop on Logic and Synthesis (IWLS)”. pp. “237–242”. “Granlibakken, CA (United States of America)”. bibtex
  • (“May” “2001”) “Gate-level simulation of CMOS circuits using the IDDM model”. In “Proc. IEEE International Symposium on Circuits and Systems (ISCAS)”. pp. “483–486”. “Darling Harbour, Sydney (Australia)”. ISBN: “0-7803-6687-5”. bibtex
  • (“March” “2001”) “HALOTIS: High Accuracy LOgic TIming Simulator with inertial and degradation delay model”. In “Proc. Conference on Design, Automation and Test in Europe (DATE)”. pp. “467–471”. “Munich (Germany)”. ISBN: “0-7695-0993-2”. bibtex

"2000" (4)

  • (“November” “2000”) “Gate-Level Modeling of the Delay Degradation Effect”. In “Proc. 15th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “537–542”. “Montpellier - Le Corum (France)”. bibtex
  • (“September” “2000”) “Influence of clocking strategies on the design of low switching-noise digital and mixed-signal VLSI circuits”. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “1918” pp. “316–326”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-41068-3”. doi bibtex
  • (“September” “2000”) “Degradation delay model extension to CMOS gates”. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “1918” pp. “149–158”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-41068-3”. doi bibtex
  • (“May” “2000”) “Inertial and Degradation Delay Model for CMOS Logic Gates”. In “Proc. IEEE International Symposium on Circuits and Systems (ISCAS)”. pp. “459–462”. “Geneva (Switzerland)”. ISBN: “0-7803-5485-0”. bibtex

Tesis doctorales

Todos (6)

  • (“2016”) “Implementación sobre hardware reconfigurable de una arquitectura no determinista, paralela y distribuida de alto rendimiento, basada en modelos de computación con membranas”. “Universidad de Sevilla”. “Advisors: A. Millan and J. Viejo”.
    • Abstract bibtex
  • (“2012”) “Técnicas de Implementación de Circuitos Integrados Digitales CMOS de Alta Velocidad de Operación y Bajo Consumo de Potencia”. “Universidad de Sevilla”. “Advisors: M. J. Bellido and J. Juan”.
    • Abstract bibtex
  • (“2011”) “Diseño e implementación sobre FPGA de sistemas digitales de bajo coste para la sincronización de equipos sobre redes de comunicación usando el protocolo SNTP”. “Universidad de Sevilla”. “Advisors: J. Juan and A. Millan”.
    • Abstract bibtex
  • (“2008”) “Técnicas de optimización para el modelado y la caracterización del comportamiento dinámico de circuitos digitales CMOS en tecnologías UDSM”. “Universidad de Sevilla”. “Advisors: M. J. Bellido and J. Juan”.
    • Abstract bibtex
  • (“2007”) “Simulación lógica temporal de altas prestaciones y aplicación a la estimación del consumo de potencia y corriente en circuitos integrados CMOS-VLSI”. “Universidad de Sevilla”. “Advisors: M. J. Bellido and J. Juan”.
    • Abstract bibtex
  • (“2000”) “Degradación del retraso de propagación en puertas lógicas CMOS VLSI”. “Universidad de Sevilla”. “Advisors: M. J. Bellido and M. Valencia”.
    • Abstract bibtex

Publicaciones docentes

"2022" (1)

  • (“June” “2022”) “Entorno de virtualización para la realización y evaluación de prácticas de laboratorio TIC”. In “Proc. 15th Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)”. pp. “628–633”. “Teruel (Spain)”. ISBN: “978-84-09-42360-6”. bibtex

"2020" (1)

  • (“July” “2020”) “Experiencia en la adaptación de una asignatura de máster para su impartición completa a distancia”. In “Proc. 14th Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)”. pp. “371–377”. “Porto (Portugal)”. ISBN: “978-989-54758-3-4”. bibtex

"2016" (1)

  • (“June” “2016”) “Metodología PBL en modo colaborativo aplicada al diseño de un SoC”. In “Proc. 12th Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)”. pp. “203–210”. “Sevilla (Spain)”. ISBN: “978-84-608-9298-4”. bibtex

"2014" (1)

  • (“June” “2014”) “Application of virtualization technology to the study of quality of service techniques”. In “Technologies Applied to Electronics Teaching (TAEE) 2014 XI”. pp. “1–6”. “Bilbao (Spain)”. ISBN: “978-1-4799-6002-6”. doi bibtex

"2012" (2)

  • (“June” “2012”) “Methodology updating experience in basic digital electronics teaching”. In “Proc. 10th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)”. pp. “52–57”. “Vigo (Spain)”. ISBN: “978-84-8158-570-4”. doi bibtex
  • (“June” “2012”) “Implementation of a hardware and software framework for a simple academic processor”. In “Proc. 10th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)”. pp. “58–63”. “Vigo (Spain)”. ISBN: “978-84-8158-570-4”. doi bibtex

"2011" (2)

  • (“2011”) “Evaluación multiagente en la formación de profesores noveles”. In “Programa de equipos docentes de la Universidad de Sevilla Cursos 2004-2005 a 2007-2008”. pp. “263–276”. “Instituto de Ciencias de la Educación, Vicerrectorado de Docencia, Universidad de Sevilla”. ISBN: “978-84-86849-37-3”. bibtex
  • (“2011”) “Experiencias del Equipo Docente de Iniciación en el Departamento de Tecnología Electrónica”. In “Programa de equipos docentes de la Universidad de Sevilla Cursos 2004-2005 a 2007-2008”. pp. “395–405”. “Instituto de Ciencias de la Educación, Vicerrectorado de Docencia, Universidad de Sevilla”. ISBN: “978-84-86849-37-3”. bibtex

"2009" (1)

  • (“2009”) “Aplicación de técnicas de evaluación continua en grupos numerosos de alumnos”. In “Experiencia de Innovación Universitaria (I)”. pp. “350–365”. “Instituto de Ciencias de la Educación, Vicerrectorado de Docencia, Universidad de Sevilla”. ISBN: “978-84-86849-70-2”. bibtex

"2008" (6)

  • (“July” “2008”) “Desarrollo de una interfaz RS-232 para el manejo de un coche de radiocontrol desde el PC”. In “Proc. 8th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)”. pp. “119”. “Zaragoza (Spain)”. ISBN: “978-84-7733-628-0”. bibtex
  • (“July” “2008”) “Ampliación de periféricos para aplicaciones embebidas basadas en hardware y software libre”. In “Proc. 5th International Conference on Telecommunications, Electronics and Control (TELEC)”. pp. “–”. “Santiago de Cuba (Cuba)”. ISBN: “978-84-00-08680-0”. bibtex
  • (“July” “2008”) “La primera experiencia en el diseño de sistemas digitales sobre FPGAs”. In “Proc. 8th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)”. pp. “161”. “Zaragoza (Spain)”. ISBN: “978-84-7733-628-0”. bibtex
  • (“July” “2008”) “Aplicación de Picoblaze al diseño de sistemas de control industrial”. In “Proc. 5th International Conference on Telecommunications, Electronics and Control (TELEC)”. pp. “–”. “Santiago de Cuba (Cuba)”. ISBN: “978-84-00-08680-0”. bibtex
  • (“July” “2008”) “Metodología de diseño SOC con OpenRISC sobre FPGA”. In “Proc. 5th International Conference on Telecommunications, Electronics and Control (TELEC)”. pp. “–”. “Santiago de Cuba (Cuba)”. ISBN: “978-84-00-08680-0”. bibtex
  • (“2008”) “Tecnología de Computadores: Asignaturas en Red. Plan de Renovación de Metodologías Docentes”. “Universidad de Sevilla”. ISBN: “978-84-691-1460-5”. bibtex

"2006" (3)

  • (“July” “2006”) “Desarrollo en VHDL de un filtro digital genérico basado en estructuras canónicas”. In “Proc. 7th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)”. pp. “285–286”. “Madrid (Spain)”. ISBN: “84-689-9590-8”. bibtex
  • (“July” “2006”) “Introducción de dispositivos programables en prácticas de laboratorio”. In “Proc. 7th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)”. pp. “135–136”. “Madrid (Spain)”. ISBN: “84-689-9590-8”. bibtex
  • (“July” “2006”) “Diseño e implementación de SOPC basados en el microprocesador PicoBlaze”. In “Proc. 7th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)”. pp. “319–320”. “Madrid (Spain)”. ISBN: “84-689-9590-8”. bibtex

"2005" (1)

  • (“2005”) “La formación del profesorado universitario”. In “Programa de equipos docentes de la Universidad de Sevilla”. pp. “75–84”. “Instituto de Ciencias de la Educación, Vicerrectorado de Calidad y Nuevas Tecnologías, Universidad de Sevilla”. ISBN: “978-84-86849-37-3”. bibtex

"2004" (6)

  • (“July” “2004”) “Diseño del microcontrolador 8051 con modulo ensamblador-generador de ROM en lenguaje VHDL”. In “Proc. 6th Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE)”. pp. “–”. “Valencia (Spain)”. ISBN: “84-688-7339-X”. bibtex
  • (“July” “2004”) “Microcontrolador 8051: compilador de ROM y diseño del micro en VHDL”. In “Proc. 3rd International Conference on Telecommunications, Electronics and Control (TELEC)”. pp. “–”. “Santiago de Cuba (Cuba)”. ISBN: “84-8138-607-3”. bibtex
  • (“July” “2004”) “Análisis del comportamiento de la videoconsola Atari 2600 como sistema digital real basado en microprocesador en el laboratorio de Electronica”. In “Proc. 6th Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE)”. pp. “–”. “Valencia (Spain)”. ISBN: “84-688-7339-X”. bibtex
  • (“July” “2004”) “ADKI: un sistema web de adquisicion de datos bajo Linux”. In “Proc. 6th Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE)”. pp. “–”. “Valencia (Spain)”. ISBN: “84-688-7339-X”. bibtex
  • (“July” “2004”) “Un sistema web para la adquisición de datos y control basado en GNU/Linux”. In “Proc. 3rd International Conference on Telecommunications, Electronics and Control (TELEC)”. pp. “–”. “Santiago de Cuba (Cuba)”. ISBN: “84-8138-607-3”. bibtex
  • (“July” “2004”) “Seguridad en Internet: Web Spoofing”. In “Proc. 6th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)”. pp. “–”. “Valencia (Spain)”. ISBN: “84-688-7339-X”. bibtex

"2003" (1)

  • (“2003”) “Desarrollo de una aplicación del área de producción animal”. In “Innovaciones Docentes en la Universidad de Sevilla”. pp. “213–218”. “Instituto de Ciencias de la Educación, Vicerrectorado de Calidad y Nuevas Tecnologías, Universidad de Sevilla”. ISBN: “84-86849-29-2”. bibtex

"2002" (2)

  • (“July” “2002”) “Design of a microprocessor for SOC applications”. In “Proc. 2nd Conferencia Internacional sobre Telecomunicación, Electrónica y Control (TELEC)”. pp. “–”. “Santiago de Cuba (Cuba)”. ISBN: “84-8138-506-9”. bibtex
  • (“February” “2002”) “Sistema de control de grupos de prácticas: aplicación al ámbito docente del Departamento de Tecnología Electrónica de la Universidad de Sevilla”. In “Proc. 5th Congreso sobre Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE)”. pp. “503–506”. “Las Palmas de Gran Canaria (Spain)”. bibtex

"2000" (2)

  • (“September” “2000”) “Concepción de un microprocesador: de la especificación a la realización”. In “Proc. 4th Congreso sobre Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE)”. pp. “565–568”. “Barcelona (Spain)”. ISBN: “84-600-9596-7”. bibtex
  • (“July” “2000”) “Aplicación de ALLIANCE al diseño de Circuitos Digitales VLSI”. In “Proc. 1st Conferencia Internacional sobre Telecomunicación, Electrónica y Control (TELEC)”. pp. “–”. “Santiago de Cuba (Cuba)”. ISBN: “84-8138-393-7”. bibtex

"1997" (1)

  • (“1997”) “Problemas de Circuitos y Sistemas Digitales”. “McGraw-Hill Interamericana, Madrid (Spain)”. ISBN: “84-481-0966-X”. bibtex
es/publications/start.txt · Última modificación: 2018/01/10 12:52 por julian

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